An arithmetic residue to binary conversion technique

Integration, the VLSI Journal

Volumn 36, Issue 1-2, 2003, Pages 13-25

  Hiasat, Ahmad A ^a  

^a PRINCESS SUMAYA UNIVERSITY FOR TECHNOLOGY   (Jordan)

Author keywords

Area; Arithmetic converter; Binary system; Residue number system; Time delay; VLSI

Indexed keywords

ADDERS; BINARY CODES; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL SIGNAL PROCESSING; VLSI CIRCUITS;

RESIDUE NUMBER SYSTEM;

CODE CONVERTERS;

EID: 0042514855     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(03)00018-X     Document Type: Article

References (20)

1. Szabo N., Tanaka R. Residue Arithmetic and its Applications to Computer Technology. 1967;McGraw-Hill, New York.
2. M. Soderstrand, M.A.W. Jenkins, G. Jullien, F. Taylor (Eds.), Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, New York, 1986.
3. Hiasat A. High-speed and reduced-area modular adder structures for RNS. IEEE Trans. Comput. 51(1):2002;84-89.
4. Hiasat A. RNS arithmetic multiplier for medium and large moduli. IEEE Trans. Circuits Systems - Part II. 47(9):2000;937-940.
5. Hiasat A. New efficient structure for a modular multiplier for RNS. IEEE Trans. Comput. 49(2):2000;170-174.
6. Keller T., Liew T.H., Hanzo L. Adaptive redundant residue number system coded multicarrier modulation. IEEE J. Selected Areas Comm. C-18(11):2000;2292-2301.
7. Chren W.A. Delta-sigma modulator with large OSR using one-hot residue number system. IEEE Trans. Circuits Systems II. 46(8):1999;1002-1008.
8. Wrzyszcz A., Milford D., Dagless E. A new approach to fixed-coefficient inner product computation over finite rings. IEEE Trans. Comput. C-47:1998;766-776.
9. Di Claudio E., Piazza F., Orlandi G. Fast combinatorial RNS processors for DSP applications. IEEE Trans. Comput. C-44:1995;624-633.
10. Premkumar A. An RNS to binary converter in a three moduli set with common factors. IEEE Trans. Circuits Systems - Part II. CAS-42:1995;298-301.
11. k-1-1) IEEE Trans. Circuits Systems - Part II. CAS-45:1998;204-209.
12. Sweidan A., Hiasat A. New efficient memoryless, residue to binary converter. IEEE Trans. Circuits Systems. CAS-35:1988;1441-1444.
13. Bernardson B. Fast memoryless, over 64 bits, residue to decimal converter. IEEE Trans. Circuits Systems. CAS-32:1985;298-300.
14. Conway R., Nelson J. Fast converter for 3 moduli RNS using new property of CRT. IEEE Trans Comput. C-48:1999;852-860.
15. k-1-1) IEEE Trans. Circuits Systems - Part II. CAS-47:2000;1576-1581.
16. n+1+1), Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Australia, April 1999, pp. 168-175.
17. n+1-1) J. Circuits Systems Comput. 10(1,2):2000;85-99.
18. A. Skavantzos, An efficient residue to weighted converter for a new residue number system, Proceedings of the Eighth Great Lakes Symposium on VLSI, Lafayette, LA, February 1998, pp. 185-191.
19. Hwang H. Computer Arithmetic: Principles, Architecture and Design. 1979;Wiley, New York.
20. Waser S., Flynn M. Introduction to Arithmetic for Digital Systems Designers. 1982;Holt, Rinehart and Winston, New York.