A higher-speed architecture for residue to binary number system conversion

International Symposium on IC Technology, Systems and Applications

Volumn 9, Issue , 2001, Pages 246-249

  Kang, Dong Hyun ^a   Ryu, Je Hyuk ^a   Cho, Jun Dong ^a  

^a The Department of Electrical and Computer Engineering   (South Korea)

Author keywords

Mixed radix conversion; Redundant to binary adder; Residue number system; Residue to binary converter

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; LOGIC CIRCUITS; NUMBER THEORY; REDUNDANCY;

BINARY NUMBER SYSTEM; MIXED RADIX CONVERSION; RESIDUE NUMBER SYSTEM; RESIDUE TO BINARY NUMBER CONVERSION;

VLSI CIRCUITS;

EID: 1842690697     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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