An Efficient VLSI Design for a Residue to Binary Converter for General Balance Moduli (2n — 3, 2n + 1, 2n — 1, 2n + 3)

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 51, Issue 3, 2004, Pages 152-155

  Sheu, Ming Hwa ^a   Lin, Su Hon ^a   Chen, Chichyang ^b   Yang, Shyue Wen ^a  

^a NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

^b FENG CHIA UNIVERSITY   (Taiwan)

Author keywords

Balanced bit width; dynamic range; moduli set; residue to binary (R B) converter; very large scale integrated circuits (VLSI) design

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; ELECTRIC CONVERTERS; TABLE LOOKUP; THEOREM PROVING; VLSI CIRCUITS; ALGORITHMS; DIGITAL ARITHMETIC; DIVIDING CIRCUITS (ARITHMETIC); INTEGRATED CIRCUIT LAYOUT; MULTIPLYING CIRCUITS;

BALANCED BIT WIDTH; BINARY CONVERTER; DIVIDE AND CONQUER TECHNIQUE; GENERAL BALANCE MODULI;

INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

BALANCED BIT WIDTH; DYNAMIC RANGE; MODULI SET; RESIDUE-TO-BINARY CONVERTER; VLSI DESIGN;

EID: 1942486712     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2003.821516     Document Type: Editorial

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