Design of a high speed reverse converter for a new 4-moduli set residue number system

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2003, Pages

  Cao, Bin ^a   Srikanthan, Thambipillai ^a   Chang, Chip Hong ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; NUMBERING SYSTEMS; SYSTEMS ANALYSIS; THEOREM PROVING;

RESIDUE NUMBER SYSTEM (RNS);

ELECTRIC CONVERTERS;

EID: 17644430795     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. N. S. Szabo and R. I. Tanaka, Residue Arithmetic and its Applications to Computer Technology. New York: McGraw Hill, 1967.
2. M. A. Soderstrand, W. K. Jenkins, G. A. Jullien and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. New York: IEEE Press, 1986.
3. S. J. Piestrak, "Design of residue generators and multioperand modular adders using carry-save adders". IEEE Trans. Comput., vol. 423, no. 1, pp. 68-77, 1994.
4. K. M. Elleithy and M. A. Bayoumi, "Fast and flexible architectures for RNS arthmetic decoding". IEEE Trans. Circuits Syst., vol. 39, no. 4, pp. 226-235, 1992.
5. F. Barsi and M. C. Pinotti, "A fully parallel algorithm for residue to binary conversion". Information Proc. Lett., vol. 50, pp. 1-8, 1994.
6. C. H. Huang, "A fully parallel mixed radix conversion algorithm for residue number applications". IEEE Trans. Comput., vol. 32, no. 4, pp. 398-402, 1983.
7. H. M. Yassine and W. R Moore, "Improved mixed-radix conversion for residue number system architectures". IEE Proc.-G,vol. 1338, no. 1, pp. 120-124, 1991.
8. S. Andraos and H. Ahmad, "A new efficient memoryless residue to binary converter". IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1441-1444, 1988.
9. S. J. Piestrak, "A high speed realization of residue to binary number system converter". IEEE Trans. Circuits Syst. -II, vol. 42, no. 10, pp. 661-663, 1995.
10. Y. Wang, "New Chinese Remainder Theorems". Proc. 32th Asilomar Conf. Signals, Syst., Comput., vol. 1, pp. 165-171, 1998.
11. n + 1)". IEEE Trans. Signal Processing, vol. 50, no. 7, pp. 1772-1779, 2002.
12. n+1 + 1}". Proc. of 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, pp. 168-175, Apr., 1999.
13. n+1 -1}". Journal of Circuits, Systems, and Computers, vol. 10, no. 1&2, pp. 85-99, 2000.
14. n + 1} moduli set". IEEE Trans. Circuits Syst. -I, vol. 45, no. 9, pp. 998-1002, 1998.