Floorplan repair using dynamic whitespace management

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 552-557

  Vorwerk, Kristofer ^a   Kennings, Andrew ^a   Chen, Doris T ^a   Behjat, Laleh ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b UNIVERSITY OF CALGARY   (Canada)

Author keywords

Floorplanning; Legalization; Placement; VLSI

Indexed keywords

ALGORITHMS; CHIP SCALE PACKAGES; SEMICONDUCTOR DEVICE MANUFACTURE; VLSI CIRCUITS;

FLOORPLANNING; LEGALIZATION; PLACEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 34748882039     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228915     Document Type: Conference Paper

References (23)

1. M. D. Moffitt, A. N. Ng, I. L. Markov, and M. E. Pollack, "Constraint-driven floorplan repair," in Proc. DAC, pp. 1103-1108, July 2006.
2. A. R. Agnihotri, S. Ono, and P. H. Madden, "Recursive bisection placement: Feng shui 5.0 implementation details," in Proc. ISPD, pp. 230-232, 2005.
3. T.-C. C. Chen, T.-C. Hsu, Z.-W. Jiang, and Y-W. Chang, "NTUplace: a ratio partitioning based placement algorithm, for large-scale mixed-size designs," in Proc. ISPD, pp. 236-238, 2005.
4. T. F. Chan, J. Cong, J. R. Shinnerl, K. S. Sze, and M. Xie, "mPL6: Enhanced multilevel mixed-size placement," in Proc. ISPD, pp. 212-214, 2006.
5. J. Cong, M. Romesis, and J. R. Shinnerl, "Fast floorplanniugby look-ahead enabled recursive bipartitioning," in Proc. ASPDAC, pp. 1119-1122, 2005.
6. B. Hu, Y. Zeng, and M. Marek-Sadowska, "mFAR: fixed-points-addition- based VLSI placement algorithm," in Proc. ISPD, pp. 239-241, April 2005.
7. K. Vorwerk, A. Kennings, and A. Vannelli, "Engineering details of a stable analytic placer," in Proc. ICCAD, 2004. 573-580.
8. A. B. Kahng, S. Reda, and Q. Wang, "Aplace: a general analytic placement framework," in Proc. ISPD, pp. 233-235, 2005.
9. U. Brenner and J. Vygen, "Legalizing a placement with minimum total movement," TCAD, vol. 23, pp. 1597-1613, 2004.
10. A. N. Ng, I. L. Markov, R. Aggarwal, and V Ramachandran, "Solving hard instances of floorplacement," in Proc. ISPD, pp. 170-177, 2006.
11. G.-J. Nam, "ISPD 2006 placement contest: Benchmark suite and results," in Proc. ISPD, pp. 167-167, 2006.
12. S. Nag and K. Chaudhary, "Post-placement residual-overlap removal with minimal movement," in Proc. DATE, 1999.
13. J. Cong and M. Xie, "A robust detailed placement for mixed-size IC designs," in Proc. ASPDAC, pp. 188-194, 2006.
14. B. A. Bell and S. K. Feiner, "Dynamic space management for user interfaces," in Proc. User Interface Soft., pp. 239-248, 2000.
15. M. Bernard and F. Jacquenet, "Free space modeling for placing rectangles without overlapping," J. of Universal Comp. Sci., vol. 3, no. 6, pp. 703-720, 1997.
16. D. Hill, "Method and system for high speed detailed placement of cells within an integrated circuit design." United States Patent 6,370,673, April 2002.
17. J.-M. Lin and Y-W. Chang, "TCG-S: orthogonal coupling of P*-admissible representations for general floorplans," in Proc. DAC, pp. 842-847, 2002.
18. H. Murata, K. Fujiyoshi, S. Nakatake, and Y Kajitani, "Rectangle-packing-based module placement," in Proc. ICCAD, pp. 472-479, 1995.
19. S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov, "Unification of partitioning, placement and floorplanniug," in Proc. ICCAD, pp. 550-557, 2004.
20. K. Vorwerk and A. Kennings, "Mixed-size placement via line search," in Proc. ICCAD, pp. 899-904, 2005.
21. T. Kong, "A novel net weighting algorithm, for timing-driven placement," in Proc. ICCAD, pp. 172-176, 2002.
22. Altera Corporation, HardCopy Series Handbook, Volume 1: Section 1: HardCopy II Device Family Data Sheet. Altera, 2005.
23. G.-J. Nam, C. J. Alpert, P. Villarrubia, B. Winter, and M. Yildiz, "The ISPD2005 placement contest and benchmark suite," in Proc. ISPD, pp. 216-220, 2005.