An analysis of wire-load model uncertainty problem

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 1, 2002, Pages 23-31

  Gopalakrishnan, Padmini ^b,c   Odabasioglu, Altan ^d   Pileggi, Lawrence ^a,c   Raje, Salil ^a  

^a IEEE

^b Monterey Design Systems   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

^d SYNOPSYS INC   (United States)

Author keywords

ASIC; CMOS; DSM; Interconnect estimation; Physical design; Wireload capacitance

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC WIRE; LOGIC DESIGN; LOGIC GATES; STATISTICAL METHODS;

LOGIC SYNTHESIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036182550     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.974134     Document Type: Article

References (13)

1. An integrated placement and synthesis approach for timing closure of PowerPC microprocessors
2. Getting to the bottom of deep submicron
3. It's the heights and not the depths that are dangerous
4. Placement and average interconnection lengths of computer logic
5. On wire-length estimations for row-based placement
6. A wire length estimation technique utilizing neighborhood density equations
7. Accurate interconnection length estimations for predictions early in the design cycle
8. Interconnection length estimation for optimized standard cell layouts
9. Average interconnection length estimation for random and optimized placements
10. Pre-layout estimation of individual wire lengths