An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 4, 2005, Pages 600-607

  Dechu, Sampath ^a   Shen, Cien ^b   Chu, Chris ^c  

^a MICRON TECHNOLOGY INC   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c Iowa State University   (United States)

Author keywords

Buffer insertion; Interconnect optimization; Steiner tree; Wire sizing

Indexed keywords

AUTOMATION; COSTS; DYNAMIC PROGRAMMING; GRAPH THEORY; HIERARCHICAL SYSTEMS; OPTIMIZATION; TREES (MATHEMATICS);

BUFFER INSERTION; INTERCONNECT OPTIMIZATION; STEINER TREES; WIRE SIZING;

ALGORITHMS;

EID: 16444367164     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.844107     Document Type: Article

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