Buffered routing tree construction under buffer placement blockages

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 381-386

  Chen, Wei ^a   Pedram, M ^a   Buch, P ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b MAGMA DESIGN AUTOMATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DELAY CIRCUITS; DYNAMIC PROGRAMMING; MULTIPROCESSING SYSTEMS; RECONFIGURABLE HARDWARE; TIMING CIRCUITS; VLSI CIRCUITS;

BUFFER INSERTION; CONVENTIONAL DESIGN; CRITICAL FACTORS; DELAY IMPROVEMENTS; GLOBAL PLACEMENTS; INTERCONNECT DELAY; PROBLEM COMPLEXITY; ROUTING TREES;

DESIGN;

EID: 84962221785     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994951     Document Type: Conference Paper

References (11)

1. L.P.P.P Van Ginneken, "Buffer Placement in Distributed RC-Tree Networks for Minimal Elmore Delay," in Proc. IEEE International Symposium on Circuits and Systems, 1990, pp. 865-868.
2. H. Zhou. D. F. Wong, I. Liu, and A. Aziz, "Simultaneous Routing and Buffer Insertion with Restriction on Buffer Location," in Proc. Design Automation Conference, 1999, pp. 96-99.
3. C. J. Alpert, "A Steiner Tree Construction for Buffers, Blockages, and Bays," IEEE Trans. On CAD of Integrated Circuits and Systems, pp. 556-562, Apr. 2001.
4. J. Cong and X. Yuan, "Routing Tree Construction Under Fixed Buffer Location," in Proc. Design Automation Conference, 2000, pp. 379-384.
5. I. Sutherland and R. Sproul, "The Theory of Logical Effort: Designing for Speed on the Back of an Envelope," Advanced Research in VLSI, Santa Cruz, 1991.
6. W. C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wide-band Amplifiers," Journal of Applied Physics, pp.55-63, 1948.
7. M. Hanan, "On Steiner's Problem with Rectilinear Distance," SIAM Journal of Applied Mathematics, pp. 255-265, 1966.
8. D. Kung, "A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries," in Proc. Design Automation Conference, 1998, pp. 352-355.
9. D. W. Hightower, "A Solution to Line-routing Problem on the Continuous Plane," in Proc. Design Automation Workshop, 1969, pp. 1-24.
10. D. Sylvester, C. Hu, O. S. Nakagawa, and S-Y. Oh, "Interconnect Scaling: Signal Integrity and Performance in Future High-speed CMOS Designs," in Proc. of VLSI symposium on Technology, 1998, pp.42-43.
11. H. Touati, "Performance-oriented Technology Mapping," Ph.D. thesis, University of California, Berkeley, Technical Report UCB.ERL M90/109, Nov. 1990.