Buffer insertion with adaptive blockage avoidance

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 492-498

  Hu, Jiang ^a   Alpert, Charles J ^b   Quay, Stephen T ^b   Gandham, Gopal ^b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b IBM   (United States)

Author keywords

Buffer insertion; Deep submicrometer; Interconnect; Layout; Physical design; Very large scale integration

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; HEURISTIC METHODS; TOPOLOGY; VLSI CIRCUITS;

ADAPTIVE BLOCKAGE AVOIDANCE; BUFFER INSERTION; DEEP SUBMICROMETER; INTERCONNECT; PHYSICAL DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037387845     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809647     Document Type: Article

References (14)

1. C. J. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," in Proc. ACM/IEEE Design Automation Conf., 1997, pp. 588-593.
2. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T Quay, and S. S. Sapatnekar, "A steiner tree construction for buffers, blockages, and bays," IEEE Trans. Computer-Aided Design, vol. 20, pp. 556-562, Apr. 2001.
3. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, and A. J. Sullivan, "Buffered steiner trees for difficult instances," IEEE Trans. Computer-Aided Design, vol. 21, pp. 3-14, Jan. 2002.
4. J. Cong., (1997) Challenges and opportunities for design innovations in nanometer technologies. SRC Design Sciences Concept Paper. [Online]. Available: http://www.src.org
5. J. Cong, T. Kong, and D. Z. Pan, "Buffer block planning for interconnect-driven floorplanning," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1999, pp. 358-363.
6. J. Cong and X. Yuan, "Routing tree construction under fixed buffer locations," in Proc. ACM/IEEE Design Automation Conf., 2000, pp. 379-384.
7. M. de Berg, M. van Kreveld, M. Overmars, and O. Schwarzkopf, Computational Geometry: Algorithms and Applications. New York: Springer-Verlag, 1997.
8. W. C. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, no. 1, pp. 55-63, 1948.
9. A. Jagannathan, S.-W. Hur, and J. Lillis, "A fast algorithm for context-aware buffer insertion," in Proc. ACM/IEEE Design Automation Conf., 2000, pp. 368-373.
10. M. Lai and D. F. Wong, "Maze routing with buffer insertion and wiresizing," in Proc. ACM/IEEE Design Automation Conf., 2000, pp. 374-378.
11. J. Lillis, C. K. Cheng, and T. Y. Lin, "Simultaneous routing and buffer insertion for high performance interconnect," in Proc. Great Lakes Symp. VLSI, 1996, pp. 148-153.
12. X. Tang, R. Tian, H. Xiang, and D. F. Wong, "A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 2001, pp. 49-56.
13. L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal elmore delay," in Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 865-868.
14. H. Zhou, D. F. Wong, I.-M. Liu, and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations," in Proc. ACM/IEEE Design Automation Conf., 1999, pp. 96-99.