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33846200137
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System-in-Silicon Architecture and its Application to H.264/AVC Motion Estimation for 1080HDTV
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Feb
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K. Kumagai, et al., "System-in-Silicon Architecture and its Application to H.264/AVC Motion Estimation for 1080HDTV," ISSCC Dig. Tech. Papers, pp. 430-431, Feb., 2006.
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Kumagai, K.1
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33846207670
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A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link
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N. Miura, et al., "A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link," ISSCC Dig. Tech. Papers, pp. 424-425, Feb., 2006.
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ISSCC Dig. Tech. Papers
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Miura, N.1
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3
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33846265502
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High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar
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Feb
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J. Yamada, et al., "High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar," ISSCC Dig. Tech. Papers, pp. 108-109, Feb., 2006.
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ISSCC Dig. Tech. Papers
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Yamada, J.1
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4
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25844471777
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A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme
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Feb
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N. Miura, et al., "A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme," ISSCC Dig. Tech. Papers, pp. 264-265, Feb., 2005.
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Miura, N.1
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5
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25844490996
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Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor
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Feb
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K. Chang, et al., "Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor," ISSCC Dig. Tech. Papers, pp. 526-527, Feb., 2005.
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ISSCC Dig. Tech. Papers
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Chang, K.1
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6
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2442675160
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Electronic Alignment for Proximity Communication
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Feb
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R. Drost, et al., "Electronic Alignment for Proximity Communication," ISSCC Dig. Tech. Papers, pp. 144-145, Feb., 2004.
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ISSCC Dig. Tech. Papers
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Drost, R.1
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7
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2442669246
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A Scalable 160Gb/s Switch Fabric Processor with 320Gb/s Memory Bandwidth
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Feb
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G. Paul, et al., "A Scalable 160Gb/s Switch Fabric Processor with 320Gb/s Memory Bandwidth," ISSCC Dig. Tech. Papers, pp. 410-411, Feb., 2004.
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ISSCC Dig. Tech. Papers
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Paul, G.1
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8
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2442653859
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A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-Chip Signaling (IIS)
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Feb
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D. Mizoguchi, et al., "A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-Chip Signaling (IIS)," ISSCC Dig. Tech. Papers, pp. 142-143, Feb., 2004.
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ISSCC Dig. Tech. Papers
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Mizoguchi, D.1
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9
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0036110464
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A 100Gb/s Transceiver with GND-VDD Common-Mode Receiver and Flexible Multi-Channel Aligner
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Feb
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K. Tanaka, et al., "A 100Gb/s Transceiver with GND-VDD Common-Mode Receiver and Flexible Multi-Channel Aligner," ISSCC Dig. Tech. Papers, pp. 264-265, Feb., 2002.
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ISSCC Dig. Tech. Papers
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Tanaka, K.1
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10
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0036224730
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A 62Gb/s Backplane Interconnect ASIC based on 3.1Gb/s Serial-Link Technology
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Feb
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P. Landman, et al., "A 62Gb/s Backplane Interconnect ASIC based on 3.1Gb/s Serial-Link Technology," ISSCC Dig. Tech. Papers, pp. 52-53, Feb., 2002.
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ISSCC Dig. Tech. Papers
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Landman, P.1
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11
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0035054795
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A 2Gb/s 21CH Low-Latency Transceiver Circuit for Inter-Processor Communication
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Feb
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T. Tanahashi, et al., "A 2Gb/s 21CH Low-Latency Transceiver Circuit for Inter-Processor Communication," ISSCC Dig. Tech. Papers, pp. 60-61, Feb., 2001.
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ISSCC Dig. Tech. Papers
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Tanahashi, T.1
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12
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0035061182
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A 28.5GB/s CMOS Non-Blocking Router for Terabit/s Connectivity between Multiple Processors and Peripheral I/O Nodes
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Feb
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R. Nair, et al., "A 28.5GB/s CMOS Non-Blocking Router for Terabit/s Connectivity between Multiple Processors and Peripheral I/O Nodes," ISSCC Dig. Tech. Papers, pp. 224-225, Feb., 2001.
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ISSCC Dig. Tech. Papers
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Nair, R.1
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13
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0034429641
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A 20Gb/s CMOS Multi-Channel Transmitter and Receiver Chip Set for Ultra-High Resolution Digital Display
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Feb
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M. Fukaishi, et al., "A 20Gb/s CMOS Multi-Channel Transmitter and Receiver Chip Set for Ultra-High Resolution Digital Display," ISSCC Dig. Tech. Papers, pp. 260-261, Feb., 2000.
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ISSCC Dig. Tech. Papers
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Fukaishi, M.1
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14
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0003528747
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110GB/s Simultaneous Bi-Directional Transceiver Logic Synchronized with a System Clock
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Feb
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T. Takahashi, et al., "110GB/s Simultaneous Bi-Directional Transceiver Logic Synchronized with a System Clock," ISSCC Dig. Tech. Papers, pp. 176-177, Feb., 1999.
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ISSCC Dig. Tech. Papers
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Takahashi, T.1
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15
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0031069052
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A 40Gb/s 8× ATM Switch LSI using 0.25μm CMOS/SIMOX
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Feb
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Y. Ohtomo, et al., "A 40Gb/s 8× ATM Switch LSI using 0.25μm CMOS/SIMOX," ISSCC Dig. Tech. Papers, pp. 154-155, Feb., 1997.
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ISSCC Dig. Tech. Papers
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Ohtomo, Y.1
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16
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0030085999
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A 5Gb/s 8×8 ATM Switch Element CMOS LSI Supporting Five Quality-of-Service Classes with 200MHz LVDS Interface
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Feb
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Y. Unekawa, et al., "A 5Gb/s 8×8 ATM Switch Element CMOS LSI Supporting Five Quality-of-Service Classes with 200MHz LVDS Interface," ISSCC Dig. Tech. Papers, pp. 118-119, Feb., 1996.
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ISSCC Dig. Tech. Papers
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Unekawa, Y.1
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17
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34548857724
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In-Situ Measurement of Supply-Noise Maps with Millivolt Accuracy and Nanosecond-Order Time Resolution
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June
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Y. Kanno, et al., "In-Situ Measurement of Supply-Noise Maps with Millivolt Accuracy and Nanosecond-Order Time Resolution," Symp. VLSI Circuits, pp. 78-79, June 2006.
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Symp. VLSI Circuits
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Kanno, Y.1
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