Power-constrained SOC test schedules through utilization of functional buses

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 230-236

  Hussin, Fawnizu Azmadi ^a   Yoneda, Tomokazu ^a   Fujiwara, Hideo ^a   Orailoglu, Alex ^b  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER DESIGNS; CORE-BASED TEST; EFFICIENT ALGORITHMS; INTERNATIONAL CONFERENCES; POWER CONSTRAINTS; RELIABILITY CHALLENGES; SOC DESIGNS; SOC TESTING;

BUSES; INTERNET; MICROPROCESSOR CHIPS; POWER GENERATION; PROGRAMMABLE LOGIC CONTROLLERS; TESTING;

BUS TRANSPORTATION;

EID: 34548735144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380822     Document Type: Conference Paper

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