-
2
-
-
85024280266
-
Merged DRAM-Logic in the year 2001
-
IEEE CS Press, Los Alamitos, Calif.
-
P.W. Diodato et al., ■Merged DRAM-Logic in the Year 2001," Proc. IEEE Int'l Workshop Memory Technology, Design and Testing (MTDT 99), IEEE CS Press, Los Alamitos, Calif., 1998, pp. 24-30.
-
(1998)
Proc. IEEE Int'l Workshop Memory Technology, Design and Testing (MTDT 99)
, pp. 24-30
-
-
Diodato, P.W.1
-
3
-
-
0026840049
-
A submicrometer CMOS embedded SRAM compiler
-
Mar.
-
J. Tou et al., "A Submicrometer CMOS Embedded SRAM Compiler," IEEE J. Solid State Circuits, vol. 27, no. 3, Mar. 1992, pp. 417-424.
-
(1992)
IEEE J. Solid State Circuits
, vol.27
, Issue.3
, pp. 417-424
-
-
Tou, J.1
-
4
-
-
0342365644
-
A widely configurable EPROM memory compiler for embedded applications
-
IEEE CS Press, Los Alamitos, Calif.
-
H. Lim et al., "A Widely Configurable EPROM Memory Compiler for Embedded Applications," Proc. IEEE Int'l Workshop Memory Technology, Design and Testing (MTDT 98), IEEE CS Press, Los Alamitos, Calif., 1998, pp. 12-16.
-
(1998)
Proc. IEEE Int'l Workshop Memory Technology, Design and Testing (MTDT 98)
, pp. 12-16
-
-
Lim, H.1
-
5
-
-
0343670885
-
Memory generator method for sizing transistor in RAM/ROM blocks
-
IEEE CS Press, Los Alamitos, Calif.
-
D. Donnelly, "Memory Generator Method for Sizing Transistor in RAM/ROM Blocks," Proc. IEEE Int'l Workshop Memory Technology, Design and Testing (MTDT 98), IEEE CS Press, Los Alamitos, Calif., 1998, pp. 10-11.
-
(1998)
Proc. IEEE Int'l Workshop Memory Technology, Design and Testing (MTDT 98)
, pp. 10-11
-
-
Donnelly, D.1
-
6
-
-
0029179413
-
Modeling application specific memories
-
IEEE CS Press, Los Alamitos, Calif.
-
D.V. Das, R. Kumar, and M. Lauria, "Modeling Application Specific Memories," Proc. IEEE Int'l Workshop on Memory Technology, Design and Testing, 1995, IEEE CS Press, Los Alamitos, Calif., pp. 10-14.
-
(1995)
Proc. IEEE Int'l Workshop on Memory Technology, Design and Testing
, pp. 10-14
-
-
Das, D.V.1
Kumar, R.2
Lauria, M.3
-
8
-
-
0027553221
-
Using march tests to test SRAMs
-
Mar.
-
A.J. van de Goor, "Using March Tests to Test SRAMs," IEEE Design and Test of Computers, vol. 10, no. 1, Mar. 1993, p. 14.
-
(1993)
IEEE Design and Test of Computers
, vol.10
, Issue.1
, pp. 14
-
-
Van De Goor, A.J.1
-
9
-
-
0023965855
-
Testing of random access memories: Theory and practice
-
Feb. IEE, Stevenage, Herts, UK
-
P.K. Veenstra, F.P.M. Beenker, and J.J.M. Koomen, "Testing of Random Access Memories: Theory and Practice," Proc. IEE, part G, vol. 135, no. 1, Feb. 1988, IEE, Stevenage, Herts, UK, pp. 24-28.
-
(1988)
Proc. IEE, Part G
, vol.135
, Issue.1
, pp. 24-28
-
-
Veenstra, P.K.1
Beenker, F.P.M.2
Koomen, J.J.M.3
-
10
-
-
0343235175
-
RAMBIST builder: A methodology for automatic built-in self-test design of embedded RAMs
-
IEEE CS Press, Los Alamitos, Calif.
-
R. Rajsuman, "RAMBIST Builder: A Methodology for Automatic Built-in Self-Test Design of Embedded RAMs," Proc. IEEE Int'l Workshop Memory Technology, Design and Testing, 1996, IEEE CS Press, Los Alamitos, Calif., pp. 50-56.
-
(1996)
Proc. IEEE Int'l Workshop Memory Technology, Design and Testing
, pp. 50-56
-
-
Rajsuman, R.1
-
11
-
-
0027610557
-
Test algorithms for double-buffered random access and pointer-addressed memories
-
June
-
J.V. Sas, F. Catthoor, and H.J. de Man, "Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories," IEEE Design and Test of Computers, vol. 10, no. 2, June 1993, pp. 34-43.
-
(1993)
IEEE Design and Test of Computers
, vol.10
, Issue.2
, pp. 34-43
-
-
Sas, J.V.1
Catthoor, F.2
De Man, H.J.3
-
12
-
-
0025414311
-
Serial interfacing for embedded memory testing
-
Apr.
-
B. Nadeau-Dostie, A. Silburt, and V.K. Agarwal, "Serial Interfacing for Embedded Memory Testing," IEEE Design and Test of Computers, vol. 7, no. 2, Apr. 1990, pp. 52-63.
-
(1990)
IEEE Design and Test of Computers
, vol.7
, Issue.2
, pp. 52-63
-
-
Nadeau-Dostie, B.1
Silburt, A.2
Agarwal, V.K.3
-
13
-
-
0343670884
-
A new test methodology for testing embedded memories in core based system-on-a-chip ICs
-
IEEE CS Press, Los Alamitos, Calif.
-
R. Rajsuman, "A New Test Methodology for Testing Embedded Memories in Core Based System-on-a-Chip ICs," Proc. IEEE Int'l Workshop Testing Embedded Cores Based System, IEEE CS Press, Los Alamitos, Calif., 1998, pp. 3.4.1-3.4.6.
-
(1998)
Proc. IEEE Int'l Workshop Testing Embedded Cores Based System
, pp. 341-346
-
-
Rajsuman, R.1
-
14
-
-
0032203003
-
Processor based built in self test for embedded DRAM
-
Nov.
-
J. Dreibelbis et al., "Processor Based Built in Self Test for Embedded DRAM," IEEE J. Solid State Circuits, vol. 33, no. 11, Nov. 1998, pp. 1,731-1,740.
-
(1998)
IEEE J. Solid State Circuits
, vol.33
, Issue.11
, pp. 1731-1740
-
-
Dreibelbis, J.1
-
15
-
-
0030736584
-
Mapping and repairing embedded memory defects
-
Jan-Mar.
-
L. Youngs and S. Paramanandam, "Mapping and Repairing Embedded Memory Defects," IEEE Design and Test of Computers, vol.14, no. 1, Jan-Mar. 1997, pp. 18-24.
-
(1997)
IEEE Design and Test of Computers
, vol.14
, Issue.1
, pp. 18-24
-
-
Youngs, L.1
Paramanandam, S.2
-
16
-
-
0343670883
-
A built-in self-repair (CRES-TA) for embedded DRAMs
-
IEEE CS Press, Los Alamitos, Calif.
-
T. Kawagoe et al., "A Built-in Self-Repair (CRES-TA) for Embedded DRAMs," Proc. IEEE Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 2000, pp. 547-556.
-
(2000)
Proc. IEEE Int'l Test Conf.
, pp. 547-556
-
-
Kawagoe, T.1
-
17
-
-
0033343253
-
Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm
-
IEEE CS Press, Los Alamitos, Calif.
-
S. Nakahara, "Built-in Self-Test for GHz Embedded SRAMs Using Flexible Pattern Generator and New Repair Algorithm," Proc. IEEE Int'l Test Conf., 1999, IEEE CS Press, Los Alamitos, Calif., pp. 301-310.
-
(1999)
Proc. IEEE Int'l Test Conf.
, pp. 301-310
-
-
Nakahara, S.1
-
18
-
-
33847146163
-
-
US patent 5577050, 1994; and US patent 5764878,1996, Patent and Trademark Office, Washington, D.C.
-
O.S. Bair et al., Method and Apparatus for Configurable Build-in Self-Repairing of ASIC Memories Design, US patent 5577050, 1994; and US patent 5764878,1996, Patent and Trademark Office, Washington, D.C..
-
Method and Apparatus for Configurable Build-in Self-Repairing of ASIC Memories Design
-
-
Bair, O.S.1
|