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Volumn 18, Issue 3, 2001, Pages 16-27

Design and test of large embedded memories: An overview

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; EMBEDDED SYSTEMS; FLASH MEMORY; LOGIC DESIGN; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; RELIABILITY; STORAGE ALLOCATION (COMPUTER);

EID: 0035339148     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.922800     Document Type: Article
Times cited : (85)

References (20)
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  • 4
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    • IEEE CS Press, Los Alamitos, Calif.
    • H. Lim et al., "A Widely Configurable EPROM Memory Compiler for Embedded Applications," Proc. IEEE Int'l Workshop Memory Technology, Design and Testing (MTDT 98), IEEE CS Press, Los Alamitos, Calif., 1998, pp. 12-16.
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    • Lim, H.1
  • 8
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    • 0023965855 scopus 로고
    • Testing of random access memories: Theory and practice
    • Feb. IEE, Stevenage, Herts, UK
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    • (1988) Proc. IEE, Part G , vol.135 , Issue.1 , pp. 24-28
    • Veenstra, P.K.1    Beenker, F.P.M.2    Koomen, J.J.M.3
  • 10
    • 0343235175 scopus 로고    scopus 로고
    • RAMBIST builder: A methodology for automatic built-in self-test design of embedded RAMs
    • IEEE CS Press, Los Alamitos, Calif.
    • R. Rajsuman, "RAMBIST Builder: A Methodology for Automatic Built-in Self-Test Design of Embedded RAMs," Proc. IEEE Int'l Workshop Memory Technology, Design and Testing, 1996, IEEE CS Press, Los Alamitos, Calif., pp. 50-56.
    • (1996) Proc. IEEE Int'l Workshop Memory Technology, Design and Testing , pp. 50-56
    • Rajsuman, R.1
  • 11
    • 0027610557 scopus 로고
    • Test algorithms for double-buffered random access and pointer-addressed memories
    • June
    • J.V. Sas, F. Catthoor, and H.J. de Man, "Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories," IEEE Design and Test of Computers, vol. 10, no. 2, June 1993, pp. 34-43.
    • (1993) IEEE Design and Test of Computers , vol.10 , Issue.2 , pp. 34-43
    • Sas, J.V.1    Catthoor, F.2    De Man, H.J.3
  • 13
    • 0343670884 scopus 로고    scopus 로고
    • A new test methodology for testing embedded memories in core based system-on-a-chip ICs
    • IEEE CS Press, Los Alamitos, Calif.
    • R. Rajsuman, "A New Test Methodology for Testing Embedded Memories in Core Based System-on-a-Chip ICs," Proc. IEEE Int'l Workshop Testing Embedded Cores Based System, IEEE CS Press, Los Alamitos, Calif., 1998, pp. 3.4.1-3.4.6.
    • (1998) Proc. IEEE Int'l Workshop Testing Embedded Cores Based System , pp. 341-346
    • Rajsuman, R.1
  • 14
    • 0032203003 scopus 로고    scopus 로고
    • Processor based built in self test for embedded DRAM
    • Nov.
    • J. Dreibelbis et al., "Processor Based Built in Self Test for Embedded DRAM," IEEE J. Solid State Circuits, vol. 33, no. 11, Nov. 1998, pp. 1,731-1,740.
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    • Dreibelbis, J.1
  • 15
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    • Mapping and repairing embedded memory defects
    • Jan-Mar.
    • L. Youngs and S. Paramanandam, "Mapping and Repairing Embedded Memory Defects," IEEE Design and Test of Computers, vol.14, no. 1, Jan-Mar. 1997, pp. 18-24.
    • (1997) IEEE Design and Test of Computers , vol.14 , Issue.1 , pp. 18-24
    • Youngs, L.1    Paramanandam, S.2
  • 16
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    • A built-in self-repair (CRES-TA) for embedded DRAMs
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  • 17
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    • S. Nakahara, "Built-in Self-Test for GHz Embedded SRAMs Using Flexible Pattern Generator and New Repair Algorithm," Proc. IEEE Int'l Test Conf., 1999, IEEE CS Press, Los Alamitos, Calif., pp. 301-310.
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    • Nakahara, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.