RFCMOS unit width optimization technique

IEEE Transactions on Microwave Theory and Techniques

Volumn 55, Issue 9, 2007, Pages 1844-1852

  Tong, Ah Fatt ^a   Lim, Wei Meng ^b   Sia, Choon Beng ^a,c   Yeo, Kiat Seng ^b   Teng, Zee Long ^a,d   Ng, Pei Fern ^a,e  

^a Advanced RFIC S Pte Ltd   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c Cascade Microtech Inc   (United States)

^d INSTITUTE OF MICROELECTRONICS   (Singapore)

^e Smar Singapore Pte Ltd   (Singapore)

Author keywords

Flicker noise; High frequency (HF) noise; Layout; Optimization; RF; RFCMOS; Unilateral power gain frequency; Unity short circuit current gain frequency

Indexed keywords

NETWORKS (CIRCUITS); OPTIMIZATION; SHORT CIRCUIT CURRENTS; SPECTRAL DENSITY; TRANSISTORS;

FIGURES-OF-MERIT (FOMS); FLICKER NOISE; GAIN FREQUENCY; HIGH-FREQUENCY (HF) NOISE; RFCMOS; UNILATERAL POWER GAIN FREQUENCY; UNIT WIDTH OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 34548523815     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2007.903348     Document Type: Article

References (33)

1. G. Weinberger, "The new millennium: Wireless technologies for a truly mobile society," in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2000, pp. 20-25.
2. E. Morifuji, H. S. MoMose, T. Ohguro, T. Yoshitomi, and H. Kimijima, "Future perspective and scaling down roadmap for RF CMOS," in VLSI Tech. Symp., 1999, pp. 163-164.
3. H. S. Momose, R. Fujimoto, S. Otaka, E. Morifuji, T. Ohguro, T. Yoshitomi, H. Kimijima, S. I. Nakamura, T. Morimoto, Y. Katsumata, H. Tanimoto, and H. Iwai, "RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the nMOS LNA circuit integrated on a chip," in Proc. VLSI Tech. Symp., Jun. 1998, pp. 96-97.
4. T. Manku, "Microwave CMOS-Device physics and design," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 277-285, Mar. 1999.
5. C. Enz, "An MOS transistor modeling for RF integrated circuit design valid in all region of operation," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 342-359, Jan. 2002.
6. C. S. Chang, C. P. Chao, J. G. J. Chern, and J. Y. C. Sun, "Advanced CMOS technology portfolio for RF IC application," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1324-1334, Jul. 2005.
7. H. S. Bennett, R. Brederlow, J. C. Costa, P. E. Cottrell, W. M. Huang, A. A. Immorlica, J. E. Mueller, M. Racanelli, H. Shichijo, C. E. Weitzel, and B. Zhao, "Device and technology evolution, for Si-based RF integrated circuits," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1235-1257, Jul. 2005.
8. H. Iwai, "CMOS technology for RF application," in Proc. 22nd Int. Microelectron. Conf., May 2000, vol. 1, pp. 27-34.
9. H. Iwai, "CMOS technology - Year 2010 and beyond," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 357-366, Mar. 1999.
10. J. Pekarik, D. Greenberg, B. Jagannathan, R. Groves, J. R. Jones, R. Singh, A. Chinthakindi, X. Wang, M. Breitwisch, D. Coolbaugh, P. Cottrell, J. Florkey, G. Freeman, and R. Krishnasamy, "RFCMOS technology from 0.25 μm to 65 nm: The state of the art," in Proc. IEEE Custom Integrated Circuits Conf., Oct. 3-6, 2004, pp. 217-224.
11. B. Jagannathan, D. Greenberg, R. Anna, X. Wang, J. Pekarik, M. Breitwisch, M. Erturk, L. Wagner, C. Schnabel, D. Sandersan, and S. Csutak, "RF FET layout and modeling for design success in RFCMOS technologies," in IEEE RF Integrated Circuits Symp. Dig., Jun. 12-14, 2005, pp. 57-60.
12. Y.-S. Lin, "An analysis of small-signal source-body resistance effect on RF MOSFETs for low-cost system-on-chip (SoC) applications," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1442-1451, Jul. 2005.
13. Y. H. Cheng, M. J. Deen, and C. H. Chen, "MOSFET modeling for RF IC design," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1286-1303, Jul. 2005.
14. W. Wu, S. Lam, and M. Chan, "Effects of layout methods of RF CMOS on noise performance," IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2753-2759, Dec. 2005.
15. Y. H. Cheng, "An overview of device behavior and modeling of CMOS technology for RF IC design," in. IEEE Int. Electron Devices for Microw. Optoelectron. Applicat. Symp., Nov. 2003, pp. 109-114.
16. K. Lee, I. Nam, I. Kwon, J. Gil, K. Han, S. Park, and B.-I. Seo, "The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1415-1422, Jul. 2005.
17. I. Bahl and P. Bhartia, Microwave Solid-State Circuit Design. New York: Wiley, 1988.
18. Y. H. Cheng, "MOSFET modeling for RF IC design," in CMOS RF Modeling, Characterization and Application. Singapore: World Sci., 2002, pp. 119-196.
19. C. H. Chen and M. J. Deen, "High frequency noise of MOSFETs I - Modeling," Solid State Electron., vol. 42, pp. 2069-2081, Nov. 1998.
20. A. V. D. Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986.
21. A. V. D. Ziel, "Thermal noise in field effect transistor," Proc. IEEE, vol. 50, no. 8, pp. 1801-1812, Aug. 1962.
22. F. Danneville, B. Iñiguez, G. Pailloncy, and G. Dambrine, "RF and noise properties of SOI MOSFETs, including the influence of a direct tunneling gate current," in Proc. 5th IEEE Int. Devices, Circuits, Syst. Conf., Caracas, Dominican Republic, Nov. 3-5, 2004, pp. 103-110.
23. G. Pailloncy, C. Raynaud, M. Vanmackelberg, F. Danneville, S. Lepilliet, J. P. Raskin, and G. Dambrine, "Impact of downscaling on high-frequency noise performance of bulk and SOI MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1605-1612, Oct. 2004.
24. H. Rothe and W. Dahlke, "Theory of noisy fourpoles," Proc. IRE, vol. 44, no. 6, pp. 811-818, Jun. 1956.
25. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 1st ed. Cambridge, U.K.: Cambridge Univ. Press, 2001, ch. 11, p. 276.
26. S. Christensson, I. Lundstrom, and C. Svensson, "Low frequency noise in MOS transistors - I. Theory," Solid State Electron., vol. 11, pp. 796-812, Sep. 1968.
27. S. Christensson, I. Lundstrom, and C. Svensson, "Low frequency noise in MOS transistors - II. Experiments," Solid State Electron., vol. 11, pp. 813-820, Sep. 1968.
28. F. M. Klaassen, "Characterization of low 1/f noise in MOS transistors," IEEE Trans. Electron Devices, vol. ED-18, no. 10, pp. 887-891, Oct. 1971.
29. G. Reimbold, "Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion-Influence of interface states," IEEE Trans. Electron Devices, vol. ED-31, no. 9, pp. 1190-1198, Sep. 1984.
30. G. Ghibaudo, "On the theory of carrier number fluctuations in MOS devices," Solid State Electron., vol. 32, pp. 563-565, 1989.
31. L. K. J. Vandamme, X. Li, and D. Rigaud, "1/f noise in MOS devices, mobility or number fluctuations?," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1936-1945, Nov. 1994.
32. X. Li, C. Barros, E. P. Vandamme, and K. L. Vandamme, "Parameter extraction and 1/f noise in a surface and a bulk-type, p-channel LDD MOSFET," Solid State Electron., vol. 37, pp. 1853-1862, Nov. 1994.
33. H. T. Friss, "Noise figures of radio receivers," Proc. IRE, vol. 32, no. 7, pp. 419-422, Jul. 1944.