RF FET layout and modeling for design success in RFCMOS technologies

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2005, Pages 57-60

  Jagannathan, B ^a   Greenberg, D ^a   Anna, R ^a   Wang, X ^a   Pekarik, J ^a   Breitwisch, M ^a   Erturk, M ^a   Wagner, L ^a   Schnabel, C ^a   Sanderson, D ^a   Csutak, S ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

De embedding; Layout; Models; Noise; RFCMOS

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COSTS; FREQUENCIES; INTEGRATED CIRCUIT LAYOUT; SPURIOUS SIGNAL NOISE; TECHNOLOGY TRANSFER;

DE-EMBEDDING; LAYOUT; NOISE; RFCMOS;

FIELD EFFECT TRANSISTORS;

EID: 27644561224     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. G Baldwin, et al., "90nm CMOS Technology for Single-Chip Radio," VLSI Tech. Dig., pp. 87-88, June 2003.
2. J. Kim, et al., "3-Dimensional Vertical Parallel Plate Capacitors in a SOI CMOS Technology for Integrated RF Circuits," VLSI Circuits Dig., pp. 29-32, June 2003.
3. R. Gillon et al., "Application of TRM Self-calibration to Standard Silicon Substrates," Proc. IEEE 2003 Int. Conf. on Microelectronic Test Structures, Vol. 16, pp. 109-112, 2003.
4. T.E. Kolding, "On-Wafer Calibration Techniques for Giga-Hertz CMOS Measurements," Proc. IEEE 1999 Int. Conf. on Microelectronic Test Structures, Vol. 12, pp. 105-110, 1999.
5. C. Chen, and M. Deen, "Channel Noise Modeling of Deep Submicron MOSFETs," IEEE Trans. Electron Devs., Vol.49, No.8, pp. 1484-1487 August 2002.