HW-SW emulation framework for temperature-aware design in MPSoCs

ACM Transactions on Design Automation of Electronic Systems

Volumn 12, Issue 3, 2007, Pages

  Atienza, David ^a,b,d   Del Valle, Pablo G ^a,b,d   Paci, Giacomo ^c   Poletti, Francesco ^c   Benini, Luca ^c   De Micheli, Giovanni ^b   Mendias, Jose M ^a,d   Hermida, Roman ^a,d  

^a UCM ^*

^b EPFL   (Switzerland)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

Emulation; FPGA; MPSoC; Temperature; Thermal aware design

Indexed keywords

COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; RELIABILITY ANALYSIS; TEMPERATURE CONTROL;

EMULATION; MULTIMEGAHERTZ SPEEDS; SYSTEM STATISTICS; THERMAL-AWARE DESIGN;

MULTIPROCESSING SYSTEMS;

EID: 34548264659     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1255456.1255463     Document Type: Conference Paper

References (36)

1. AMD. 2004. Thermal performance comparison for am486dx2 and dx4 in pdh-208 vs pde-208 package. http://www.amd.com.
2. APTIX. 2003. System explore. http://www.aptix.com.
3. ARM. 2003. Arm AMBA 2 AHB Specification. http://www.arm.com/products/ solutions/AMBA_Spec.html.
4. ARM. 2004a. Arm integrator application. http://www.arm.com.
5. ARM. 2004b. ARM7TDMI-STR71xF TQFP144 and TQFP64 10×10 packages - Product datasheets. http://www.arm.com/products/CPUs/ARM7TDMT.html.
6. ARM. 2002. PrimeXSys platform architecture and methodologies, white paper. http://www.arm.com/pdfs/ARM11%20Core%20%20Platform%20Whitepaper.pdf.
7. BENINI, L., BERTOZZI, D., BOGLIOLO, A., MENICHELLI, F., AND OLIVIERI, M. 2005. Mparm: Exploring the multiprocessor SoC design space with SystemC. J. VLSI Signal Process. 41, 2, 169-182.
8. BRAUN, G., WIEFERINK, A., SCHLIEBUSCH, O., LEUPERS, R., MEYR, H., AND NOHL, A. 2003. Processor/ Memory co-exploration on multiple abstraction levels. In Proceedings of the DATE.
9. BROOKS, D. AND MARTONOSI, M. 2001. Dynamic thermal management for high-performance microprocessors. In Proceedings of the HPCA.
10. CADENCE. 2005. Cadence palladium II. http://www.cadence.com.
11. CHEN, G. AND SAPATNEKAR, S. 2003. Partition-Driven standard cell thermal placement. In Proceedings of the ISPD.
12. CHU, C. AND WONG, D. 1998. A matrix synthesis approach to thermal placement. IEEE Trans. Comput. Aided Des. 17, 11, 1166-1174.
13. COWARE. 2004. Convergence and Lisatek product lines.
14. EMULATION AND VERIFICATION ENGINEERING. 2005. Zebu XL and ZV models. http://www.eve-team.com.
15. GOPLEN, B. AND SAPATNEKAR, S. 2005. Thermal via placement in 3D ICs. In Proceedings of the ISPD.
16. HEO, S., BARR, K., AND ASANOVIC, K. 2003. Reducing power density through activity migration. In Proceedings of the ISLPED.
17. HERON ENGINEERING. 2004. Heron MPSoC emulation. http://www.hunteng.co.uk.
18. IBM. 2006. IBM packaging solutions. http://www-03.ibm.com/chips/asics/ products/packaging.html.
19. JALABERT, A., MURALI, S., BENINI, L., AND DE MICHELI, G. 2004. xpipescompiler: A tool for instantiating application specific networks-on-chip. In Proceedings of the DATE.
20. JERRAYA, A. AND WOLF, W. 2005. Multiprocessor Systems-on-Chips. Morgan Kaufmann, Elsevier.
21. LÓPEZ-BUEDO, S., GARRIDO, J., AND BOEMO, E. I. 2000. Thermal testing on reconfigurable computers. IEEE Des. Test Comput. 17, 1, 84-91.
22. MAGNUSSON, P. S., CHRISTENSSON, M., ESKILSON, J., FORSGREN, D., HALLBERG, G., HOGBERG, J., LARSSON, F., MOESTEDT, A., AND WERNER, B. 2002. Simics: A full system simulation platform. IEEE Comput. 35, 2, 50-58.
23. MENTOR GRAPHICS. 2003. Platform express and Primecell. http://www.mentor.com/products/embedded_software/platform_baseddesign/.
24. NAKAMURA, Y., HOSOKAWA, K., KURODA, I., YOSHIKAWA, K., AND YOSHIMURA, T. 2004. A fast HW/SW co-verification method for SoC by using a C/C++ simulator and FPGA emulator with shared register communication. In Proceedings of the DAC.
25. NAVA, M. D., BLOUET, P., TENINGE, P., COPPOLA, M., BEN-ISMAIL, T., PICCHIOTTINO, S., AND WILSON, P. 2005. An open platform for developing MPSoC. IEEE Comput., 60-67.
26. PACI, G., MARCHAL, P., POLETTI, F., AND BENINI, L. 2006. Exploring temperature-aware design in low-power MPSoCs. In Proceedings of the DATE.
27. PAULIN, P., PILKINGTON, C., AND BENSOUDANE, E. 2002. Stepnp: A system-level exploration platform for network processors. IEEE Des. Test 19, 6, 17-26.
28. R. W. FLOYD, E. A. 1985. Adaptive algorithm for spatial gray scale. In Proceedings of the ISDT.
29. ROHOU, E. AND SMITH, M. 1999. Dynamically managing processor temperature and power. In Proceedings of the FDO.
30. SEMICONDUCTOR INDUSTRY ASSOCIATION (SIA). 2004. The international technology roadmap for semiconductors. http://public.itrs.net/.
31. SKADRON, K., STAN, M., HUANG, W., VELUSAMY, S., SANKARANARAYANAN, K., AND TARJAN, D. 2002. Thermal-RC modeling for accurate and localized dynamic TM. In Proceedings of the HPCA.
32. SKADRON, K., STAN, M. R., SANKARANARAYANAN, K., HUANG, W., VELUSAMY, S., AND TARJAN, D. 2004. Temperature-Aware microarchitecture: Modeling and implementation. Trans. Architecture Code Optimizations 1, 1, 94-125.
33. SRINIVASAN, J. AND ADVE, S. V. 2003. Predictive dynamic thermal management for multimedia applications. In Proceedings of the ICS.
34. SU, H., LIU, F., DEVGAN., A., ACAR, E., AND NASSIF, S. 2003. Full chip leakage estimation considering power supply and temperature variations. In Proceedings of the ISLPED. 78-83.
35. SYNOPSYS. 2003. Realview maxsim ESL environment. http://www.- synopsys.com.
36. VANDEVELDE, B., DRIESSENS, E., CHANDRASEKHAR, A., AND BEYNE, E. 2001. Characterisation of the polymer stud grid array, a lead-free CSP for high performance and high reliable packaging. In Proceedings of the SMTA.