An open platform for developing multiprocessor SoCs

Computer

Volumn 38, Issue 7, 2005, Pages 60-67

  Diaz Nava, Mario ^a   Blouet, Patrick ^a   Teninge, Philippe ^a   Coppola, Marcello ^a   Ben Ismail, Tarek ^a   Picchiottino, Samuel ^a   Wilson, Robin ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); NANOTECHNOLOGY; NETWORK PROTOCOLS; SOFTWARE ENGINEERING;

MULTIPROCESSOR SYSTEM-ON-CHIP (MPSOC) DESIGNS; SOFTWARE SIMULATION;

MICROPROCESSOR CHIPS;

EID: 22944443872     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2005.218     Document Type: Article

References (9)

1. A. Sangiovanni-Vincentelli et al., "Benefits and Challenges for Platform-Based Design," Proc. 41st Design Automation Conf., IEEE Press, 2004, pp. 409-414.
2. W. Cesario et al., "Multiprocessor SoC Platforms: A Component-Based Design Approach," IEEE Design and Test of Computers, Nov.-Dec. 2002, pp. 52-63.
3. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," Computer, Jan. 2002, pp. 70-78.
4. N. Ohba and K. Takano, "An SoC Design Methodology Using FPGAs and Embedded Microprocessors," Proc. 41st Design Automation Conf., IEEE Press, 2004, pp. 747-752.
5. M.W. Youssef et al., "Debugging HW/Software Interface for MPSoC: Video Encoder System Design Case Study," Proc. 41st Design Automation Conf., IEEE Press, 2004, pp. 908-913.
6. D. Culler, J.P. Singh, and A. Gupta, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann, 1999.
7. STMicroelectronics, "STBus Functional Specifications," Apr. 2003, http://mcu.st.com/mcu/inchtml.php?fdir=pages&fnam=StBus_intro.
8. S. Picchiottino, R. Wilson, and M. Diaz Nava, "Platform to Validate System on Chip Design Flows and Methodologies," Proc. IP-Based SoC Design Conf., Design and Reuse, Grenoble, France, 2004, pp. 39-44,
9. S-I. Han et al., "An Efficient Scalable and Flexible Data Transfer Architecture for a Multiprocessor SoC with Massive Distributed Memory," Proc. 41st Design Automation Conf., IEEE Press, 2004, pp. 250-255.