Processor/memory co-exploration on multiple abstraction levels

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 966-971

  Braun, Gunnar ^a   Wieferink, Andreas ^a   Schliebusch, Oliver ^a   Leupers, Rainer ^a   Meyr, Heinrich ^a   Nohl, Achim ^b  

^a Integrated Signal Processing Systems   (Germany)

^b LISATek Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTION LEVEL; APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR (ASIP); ARCHITECTURE DESCRIPTION LANGUAGES; EFFICIENT DESIGNS; EXPLORATION PROCESS; HETEROGENEOUS MEMORY; MEMORY SUBSYSTEMS; SINGLE-CHIP SOLUTIONS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; EMBEDDED SYSTEMS; EXHIBITIONS; PROGRAMMABLE LOGIC CONTROLLERS;

MEMORY ARCHITECTURE;

EID: 84893726874     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253730     Document Type: Conference Paper

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