Reducing delay uncertainty of on-chip interconnects by combining inverting and non-inverting repeaters insertion

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Volumn , Issue , 2007, Pages 219-224

  Akl, Charbel J ^a   Bayoumi, Magdy A ^a  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MICROPROCESSOR CHIPS; UNCERTAINTY ANALYSIS;

DELAY UNCERTAINTY MINIMIZATION; ON-CHIP INTERCONNECTS; REPEATER INSERTION;

INTERCONNECTION NETWORKS;

EID: 34548125240     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.134     Document Type: Conference Paper

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