Formal derivation of optimal active shielding for low-power on-chip buses

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 5, 2006, Pages 821-835

  Ghoneima, Maged ^a,b   Ismail, Yehea I ^a,b   Khellah, Muhammad M ^a,c,d   Tschanz, James W ^a,c,e   De, Vivek ^a,c  

^a IEEE   (United States)

^b NORTHWESTERN UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

^d Intel's Microprocessor Technology Labs

^e OREGON HEALTH AND SCIENCE UNIVERSITY   (United States)

Author keywords

Capacitive coupling; Interconnects; Low power design; On chip bus; Shielding

Indexed keywords

CAPACITIVE COUPLING; LOW POWER DESIGN; ON-CHIP BUS;

BUSBARS; CAPACITANCE; ENERGY CONSERVATION; ENERGY DISSIPATION; LOGIC DEVICES; MICROPROCESSOR CHIPS; SWITCHING;

ELECTRIC SHIELDING;

EID: 33646424150     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.855974     Document Type: Conference Paper

References (19)

1. D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, no. 6. pp. 663-670, Jun. 1994.
2. R. Kumar, "Interconnect and noise immunity design for the Pentium 4 processor," Intel Technol. J., vol. 5. no. 1, pp. 1-12, Feb. 2001.
3. Y. Shin and T. Sakurai, "Coupling-driven bus design for low-power application-specific sys.," in Proc. Design Automation Conf. (DAC), Las Vegas, NV, 2001, pp.750-753.
4. P. Saxena and C. Liu, "A postprocessing algorithm for crosstalk-driven wire perturbation," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 6, pp. 691-702. Jun. 2000.
5. L. Macchiarulo, E. Macii, and M. Poncino, "Wire placement for crosstalk energy minimization in address buses." in Proc. Design, Automation and Test Eur. (DATE), Paris, France, Mar. 2002, pp. 158-162.
6. E. Macii, M. Poncino, and S. Salerno, "Combining wire swapping and spacing for low-power deep-submicron buses." in Proc. IEEE 12th Great Lakes Symp. VLSI(GLS-VLSI), Washington, DC, Apr. 2003, pp. 198-202.
7. P. Gupta and A. Kahng, "Wire swizzling to reduce delay uncertainty due to cap. coupling," in Proc, Int. Conf. VLSI Design, Mumbai, India, Jan. 2004, pp. 431-436.
8. A. B. Kahng et al., "Interconnect tuning strategies for high performance ICs." in Proc. Design Automation and Test Eur, (DATE), Paris, France, 1998. pp. 471-178.
9. K. Hirose and H. Yasuura, "A bus delay reduction technique considering crosstalk," in Proc. Design Automation and Test Eur. (DATE), Paris, France, 2000, pp. 441-145.
10. A. Vittal and M. Sadowska, "Crosstalk reduction for VLSI." IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 16, no. 3. pp. 290-298, Mar. 1997.
11. H. Kaul, D. Sylvester, and D. Blauw, "Active shields: A new approach to shielding global wires." in Proc. Great Lakes Symp. VLSI (GLS-VLSI), New York, 2002, pp. 112-117.
12. L. Van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. Int. Symp. Circuits and Systems (ISCAS), New Orleans, LA, 1990, vol. 2, pp. 865-868.
13. C. J. Alpert, A. Devgna, and S. Quay, "Buffer insertion for noise and delay optimization," IEEE Trans. Comput.-Aided Des, Integr. Circuits Syst., vol. 18, no. 11, pp. 1633-1645, Nov. 1999.
14. D. Kirkpatrick and A. Vincentelli, "Techniques for crosstalk avoidance in the physical design of high-performance digital systems," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, 1994, pp. 616-619.
15. P. Sotiriadis and A. Chandrakasan, "A bus energy model for deep submicron technology," IEEE Trans. Very Large Scale Integr, (VLSI) Syst., vol. 10. no. 3, pp. 341-350, Jun. 2002.
16. M. Stan and W. P. Burieson, "Bus-invert coding for low-power I/O," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3. no. 1, pp. 49-58, Mar. 1995.
17. M. Khellah, J. Tscahnz, Y. Ye, S. Narendra, and V. De, "Static pulsed bus for on-chip interconnects," in Proc. VLSI Symp., Honolulu, HI. Jun. 2002, pp. 78-79.
18. M. Ghoneima and Y. Ismail, "Effect of relative delay on the dissipated energy in coupled interconnects," in Proc. Int. Symp, Circuits and Systems, Vancouver, Canada, May 2004. vol. 2, pp. 525-528.
19. R. Arunachalam, E. Acar, and S. Nassif, "Optimal shielding/spacing metrics for low power design," in Proc. Annu Symp. VLSI (ISVLSI), Tampa. FL, 2003, pp. 167-172.