-
1
-
-
84948774920
-
Exploiting Pseudo-schedules to Guide Data Dependence Graph Partitioning
-
A. Aletà, J.M. Codina, J. Sánchez, A. González, and D. Kaeli, "Exploiting Pseudo-schedules to Guide Data Dependence Graph Partitioning", in Proc. of the 2002 Int. Conf. on Parallel Architectures and Compiler Techniques.
-
Proc. of the 2002 Int. Conf. on Parallel Architectures and Compiler Techniques
-
-
Aletà, A.1
Codina, J.M.2
Sánchez, J.3
González, A.4
Kaeli, D.5
-
2
-
-
84944394490
-
Instruction Replication for Clustered Microarchitectures
-
A. Aletà, J.M. Codina, A. González, and D. Kaeli, "Instruction Replication for Clustered Microarchitectures", in Proc. of 36th Int. Symp. on Microarchitecture, 2003.
-
(2003)
Proc. of 36th Int. Symp. on Microarchitecture
-
-
Aletà, A.1
Codina, J.M.2
González, A.3
Kaeli, D.4
-
4
-
-
0019398205
-
Register Allocation Via Coloring
-
G.J. Chaitin, M.A. Auslander, A.K. Chandra, J. Cocke, M.E. Hopkins, and P.W. Markstein, "Register Allocation Via Coloring", Computer Languages, 1981.
-
(1981)
Computer Languages
-
-
Chaitin, G.J.1
Auslander, M.A.2
Chandra, A.K.3
Cocke, J.4
Hopkins, M.E.5
Markstein, P.W.6
-
5
-
-
0026157612
-
IMPACT: An Architectural Framework for Multiple- Instruction-Issue Processors
-
P.P. Chang, S.A. Mahlke, W.Y. Chen, N.J. Water, and W.W. Hwu, "IMPACT: An Architectural Framework for Multiple- Instruction-Issue Processors", in Proc. of the 18th Int. Symp. on Computer Architecture, 1991.
-
(1991)
Proc. of the 18th Int. Symp. on Computer Architecture
-
-
Chang, P.P.1
Mahlke, S.A.2
Chen, W.Y.3
Water, N.J.4
Hwu, W.W.5
-
8
-
-
34547703520
-
-
J.M. Codina, J. Sánchez, and A. González, Virtual Cluster Scheduling Through the Scheduling Graph, Tech. Report UPC-DAC-RR-ARCO-2005-6, Dep. of Computer Architecture, UPC, Barcelona.
-
J.M. Codina, J. Sánchez, and A. González, "Virtual Cluster Scheduling Through the Scheduling Graph", Tech. Report UPC-DAC-RR-ARCO-2005-6, Dep. of Computer Architecture, UPC, Barcelona.
-
-
-
-
9
-
-
0031999322
-
Instruction Assignment for Clustered VLIW DSP Compilers: A New Approach
-
Technical Report HPL-98-13, HP Laboratories
-
G. Desoli, "Instruction Assignment for Clustered VLIW DSP Compilers: A New Approach", Technical Report HPL-98-13, HP Laboratories, 1998.
-
(1998)
-
-
Desoli, G.1
-
10
-
-
34547703688
-
Bulldog: A Compiler for VLIW Architectures
-
R. Ellis, "Bulldog: A Compiler for VLIW Architectures", MIT Press, pp. 180-184, 1986.
-
(1986)
MIT Press
, pp. 180-184
-
-
Ellis, R.1
-
11
-
-
0033703885
-
Lx: A Technology Platform for Customizable VLIW Embedded Processing
-
P. Faraboschi, G. Brown, J. Fisher, G. Desoli, and F. Homewood, "Lx: A Technology Platform for Customizable VLIW Embedded Processing", in Proc. of the 27th Int. Symp on Computer Architecture, 2000.
-
(2000)
Proc. of the 27th Int. Symp on Computer Architecture
-
-
Faraboschi, P.1
Brown, G.2
Fisher, J.3
Desoli, G.4
Homewood, F.5
-
13
-
-
0033888003
-
The TigerSharc DSP Architecture
-
Jan-Feb
-
J. Fridman, and Z. Greenfield, "The TigerSharc DSP Architecture", IEEE Micro, pp. 66-76, Jan-Feb. 2000.
-
(2000)
IEEE Micro
, pp. 66-76
-
-
Fridman, J.1
Greenfield, Z.2
-
16
-
-
0027595384
-
The Superblock: An Effective Technique for VLIW and Superscalar Compilation
-
W. Hwu et al, "The Superblock: An Effective Technique for VLIW and Superscalar Compilation", Journal of Supercomp., v.7 n.1/2, 1993.
-
(1993)
Journal of Supercomp
, vol.7
, Issue.1-2
-
-
Hwu, W.1
-
17
-
-
0003276936
-
A Code Generation Framework for VLIW Architectures with Partitioned Register Banks
-
S. Jang, S. Carr, P. Sweany, and D. Kuras, "A Code Generation Framework for VLIW Architectures with Partitioned Register Banks", in Proc. of 3rd. Int. Conf. on Massively Parallel Computing Systems, 1998.
-
(1998)
Proc. of 3rd. Int. Conf. on Massively Parallel Computing Systems
-
-
Jang, S.1
Carr, S.2
Sweany, P.3
Kuras, D.4
-
20
-
-
0036660095
-
Cluster Assignment for High-Performance Embedded VLIW Processors
-
July
-
V.S. Lapinskii, M. F. Jacome, G.A. Veciana, "Cluster Assignment for High-Performance Embedded VLIW Processors", in ACM Trans. on Design Automation of Electronic Systems, Vol. 7, No. 3, July 2002.
-
(2002)
ACM Trans. on Design Automation of Electronic Systems
, vol.7
, Issue.3
-
-
Lapinskii, V.S.1
Jacome, M.F.2
Veciana, G.A.3
-
21
-
-
33646745855
-
Convergent Scheduling
-
W. Lee, D. Puppin, S. Swenson, and S. Amarasinghe, "Convergent Scheduling", in Proc. of 35th Int. Symp. on Microarchitecture, 2002.
-
(2002)
Proc. of 35th Int. Symp. on Microarchitecture
-
-
Lee, W.1
Puppin, D.2
Swenson, S.3
Amarasinghe, S.4
-
22
-
-
0005000036
-
LEDA, a library of efficient data types and algorithms
-
04/89, Universität des Saarlandes, Saarbrücken
-
K. Mehlhorn and S. Näher, "LEDA, a library of efficient data types and algorithms", Tech. Report TR A 04/89, Universität des Saarlandes, Saarbrücken, 1989.
-
(1989)
Tech. Report TR A
-
-
Mehlhorn, K.1
Näher, S.2
-
24
-
-
0032308536
-
Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures
-
E. Özer, S. Banerjia, and T. Conte, "Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures", In Procs. of the 31st Int. Symp. on Microarchitecture, 1998.
-
(1998)
Procs. of the 31st Int. Symp. on Microarchitecture
-
-
Özer, E.1
Banerjia, S.2
Conte, T.3
-
27
-
-
18844430522
-
Cluster assignment of global values for clustered VLIW processors
-
A. Terechko, E. Le Thenaff, and H. Corporaal, "Cluster assignment of global values for clustered VLIW processors", in Proc. of the 2003 Int.Conf. on Compilers, Architecture, and Synthesis for Embedded Systems.
-
Proc. of the 2003 Int.Conf. on Compilers, Architecture, and Synthesis for Embedded Systems
-
-
Terechko, A.1
Le Thenaff, E.2
Corporaal, H.3
|