The ManArray™ embedded processor architecture

Conference Proceedings of the EUROMICRO

Volumn 1, Issue , 2000, Pages 348-355

  Pechanek, Gerald G ^a   Vassiliadis, Stamatis ^b  

^a Billions of Operations Per Second (BOPS) Inc   (United States)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CONDITIONAL EXECUTION; DISTRIBUTED ARRAYS; EMBEDDED PROCESSOR ARCHITECTURE; EMBEDDED PROCESSORS; HIGH CONNECTIVITY; HIGH PERFORMANCE ALGORITHMS; MULTIPLE CONFIGURATIONS; PROCESSING ELEMENTS;

COMPLEX NETWORKS; NETWORK ARCHITECTURE; PARALLEL PROCESSING SYSTEMS;

COMPUTER ARCHITECTURE;

EID: 84889241806     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.2000.874652     Document Type: Conference Paper

References (17)

1. SGS Thomson Microelectronics, MPEG audio/MPEG-2 ideo intergrated decoder Sti3520. http://www. st. com. October 1996.
2. SGS Thomson Microelectronics, MPEG 2. 5 Layer III audio decoder STA013. http://www. st. com, September 1999.
3. A. Van Roermond, P. Snijder, H. Dijkstra, C. Hemeryck, C. Huizer, J. Schimtz, and R. Sluijter. A Genera;-Purpose Programmable Video Signal Processor. IEEE Transactions on Consumer electronics, 1989.
4. J. Goto, K. Ando, T. Inoue, M. Yamashina, H. Yamada, and T. Enomoto. 250-Mhz BiCMOS Super-High-Speed Video Signal Processor (S-VSP) ULSI. IEEE Journal of Solid-State Circuits, 1991.
5. P. A. Ruetz, P. Tong, D. Bailey, D. A. Luthi, and P. H. Ang. A High-Performance Full-Motion Video Compression Chip Set. IEEE Transactions on Circuits and Systems for Video Technology, 1992.
6. S. Rathnam and G. Slavenburg. An Architectural Overview of the Programmable Multimedia Processor, TM-1. In Proceedings ofCOMPCON '96, pages 319-326. IEEE, 1996.
7. K. Guttag, R. J. Gove, and J. R. van Aken. A single-chip multiprocessor for multimedia: The MVP, IEEE Computer Graphics and Applications, November 1992.
8. A. Peleg and U. Weiser. MMX Technology Extension to the Intel Architecture. IEEE Micro, 16(4):42-50, August 1996.
9. P. Rubinfeld, B. Rose, and M. McCallig. Motion Video Instruction Extensions for Alpha, http://www. di eital. coni/semiconductor/papers/pmvi- abstract. htm, October 1996.
10. M. Tremblay, J. M. O'Conner, V. Narayanan, and L. He. Vis speeds new media processing. IEEE Micro, 16(4):10-20, August 1996
11. MIPS digital media extension. http://iiww. sai. cor,-lPS/i)rorlrrct
12. G. G. Pechanek, S. Vassiliadis, N. Pitsianis. ManArray Processor Interconnection Network: An Introduction. In Proceedings of 5" Int'l EURO-PAR Conference Toulouse, France, AugusUSeptember 1999
13. BOPS, Inc., BOPS 2040 core data sheet, http://boprnet. com/cor-\ bops2OJO. shlml
14. BOPS, Inc., BOPS benchmarks, httn:/lbonsnet. com/benchmark-. shtml
15. G. G. Pechanek, B. Schulman, and C. Kurak. Design of MPEG-2 Function with Embedded ManArray Cores. In Proceedings of DesignCon 2000 IP World Forum Santa Clara, Califomia, JanuaryFebruary 2000.
16. N. P. Pitsianis and G. Pechanek. High-Performance FFT Implementation on the BOPS ManArray Parallel DSP. In proceedings Intemational Symposium on Optical Science, Engineering, and Instrumentation, Denver, Colorado, July, 1999.
17. BOPS, Inc., BOPS Software Development Kit (SDK), http://bopsnet. com/lools. shtinl