The effectiveness of loop unrolling for modulo scheduling in clustered VLIW architectures

Proceedings of the International Conference on Parallel Processing

Volumn 2000-January, Issue , 2000, Pages 555-562

  Sanchez J ^a   Gonzalez A ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Communication channels; Computer architecture; Continuous improvement; Delay effects; Electronic mail; Pipeline processing; Processor scheduling; Proposals; Registers; VLIW

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; ELECTRONIC MAIL; PIPELINE PROCESSING SYSTEMS; SCHEDULING;

CONTINUOUS IMPROVEMENTS; DELAY EFFECTS; PIPELINE PROCESSING; PROCESSOR SCHEDULING; PROPOSALS; REGISTERS; VLIW;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84949503766     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2000.876173     Document Type: Conference Paper

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