ID-VGS-based tools to profile charge distributions on NROM memory devices

IEEE Transactions on Device and Materials Reliability

Volumn 7, Issue 1, 2007, Pages 97-104

  Padovani, Andrea ^a,b   Larcher, Luca ^a,c   Pavan, Paolo ^a,c   Avital, Lior ^d   Bloom, Ilan ^d   Eitan, Boaz ^a,d  

^a IEEE   (Italy)

^b UNIVERSITY OF FERRARA   (Italy)

^c UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^d Saifun Semiconductors   (Israel)

Author keywords

Device simulations; Flash memory; Gate induced drain leakage (GIDL); Nitride based trapping storage; NROM; Semiconductor device reliability; Trapped charge profiling

Indexed keywords

DEVICE SIMULATIONS; GATE-INDUCED DRAIN LEAKAGE (GIDL); NITRIDE-BASED TRAPPING STORAGE; SEMICONDUCTOR DEVICE RELIABILITY; TRAPPED CHARGE PROFILING;

CHARGE DISTRIBUTION; CHARGE TRAPPING; COMPUTER SIMULATION; NITRIDES; OPTIMIZATION; RELIABILITY THEORY;

DATA STORAGE EQUIPMENT;

EID: 34547186406     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2007.897528     Document Type: Conference Paper

References (21)

1. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, Nov. 2000.
2. L. Larcher, P. Pavan, and B. Eitan, "On the physical mechanism of the NROM memory erase," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1593-1599, Oct. 2004.
3. A. Shappir, E. Lusky, G. Choen, I. Bloom, M. Janai, and B. Eitan, "The two-bit NROM reliability." IEEE Trans. Device Mater. Rel., vol. 4. no. 3, pp. 397-403, Sep. 2004.
4. B. Eitan, G. Cohen, A. Shappir, E. Lusky, A. Givant, M. Janai, I. Bloom, Y. Polansky, O. Dadashev, A. Lavan, R. Sahar, and E. Maayan, "4-bit per cell NROM reliability," in IEDM Tech. Dig., Washington, DC, Dec. 5-8, 2005, pp. 539-542.
5. M. Janai and B. Eitan, "Data retention, endurance and acceleration factors of NROM devices," in Proc. IEEE Int. Rel. Phys. Symp., Apr. 2003, vol. 41, pp. 502-505.
6. M. Janai, B. Eitan, A. Shappir, E. Lusky, I. Bloom, and G. Cohen, "Data retention reliability model of NROM nonvolatile memory products," IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 404-415, Sep. 2004.
7. E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, "Electrons retention model for localized charge in oxide-nitride-oxide (ONO) dielectric," IEEE Electron Device Lett., vol. 23, no. 9, pp. 556-558, Sep. 2002.
8. M. Rosmeulen, L. Breuil, M. Lorenzini, L. Haspeslagh, J. Van Houdt, and D. De Meyer, "Characterization of the spatial charge distribution in local charge-trapping memory devices using the charge-pumping technique," Solid State Electron., vol. 48, no. 9, pp. 1525-1530, Sep. 2004.
9. P. B. Kumar, P. R. Nair, R. Sharma, S. Kamohara, and S. Mahapatra, "Lateral profiling of trapped charge in SONOS flash. EEPROMs programmed using CHE injection," IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 698-705, Apr. 2006.
10. A. Furnémont, M. Rosmeulen, J. Van Houdt, H. Maes, and K. De Meyer, "Cycling behaviour of nitride charge profile in NROM-type memory cells," in Proc. 21st Non-Volatile Semicond Memory Workshop, Feb. 2006, pp. 66-67.
11. E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, "Characterization of channel hot electron injection by the subthreshold slope of NROM device," IEEE Electron Device Lett., vol. 22, no. 11, pp. 556-558, Nov. 2001.
12. L. Larcher, G. Verzellesi, P. Pavan, E. Lusky, I. Bloom, and B. Eitan, "Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1939-1946, Nov. 2002.
13. A. Shappir, Y. Shacham-Diamand, E. Lusky, I. Bloom, and B. Eitan, "Subthreshold slope degradation model for localized-charge-trapping based on non-volatile memory devices," Solid State Electron., vol. 47, no. 5, pp. 937-941, May 2003.
14. A. Shappir, D. Levi, Y. Shacham-Diamand, E. Lusky, I. Bloom, and B. Eitan, "Spatial characterization of localized charge trapping and charge redistribution in the NROM device," Solid State Electron., vol. 48, no. 9, pp. 1489-1495, Sep. 2004.
15. S. Mahapatra, S. Shukuri, and J. Bude, "CHISEL flash EEPROM-Part I: Performance and scaling," IEEE Trans. Electron Devices, vol. 49, no. 7, pp. 1296-1301, Jul. 2002.
16. Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1987.
17. C. Lombardi, S. Manzini, A. Saporito, and M. Vanzini, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 7, no. 11, pp. 1164-1171, Nov. 1988.
18. L. Avital, A. Padovani, L. Larcher, I. Bloom, R. Arie, P. Pavan, and B. Eitan, "Temperature monitor: A new tool to profile charge distribution, in NROM memory devices," in Proc. IEEE Int. Rel. Phys. Symp., San Jose, CA, 2006, vol. 44, pp. 534-540.
19. M.-Y. Liu, Y-W. Chang, N.-K. Zous, I. Yang, T.-C. Lu, T. Wang, W. Ting, J. Cu, and C-Y. Lu, "Temperature effect on read current in a two-bit nitride-based trapping storage flash EEPROM cell," IEEE Electron Device Lett., vol. 25, no. 7, pp. 495-497, Jul. 2004.
20. A. Padovani, L. Larcher, and P. Pavan, "Profiling charge distributions in NROM devices," in Proc. PRIME, Jun. 2006, pp. 69-72.
21. M. Grabe, Measurement Uncertainties in Science and Technology. Berlin, Germany: Springer-Verlag, Apr. 2005.