Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection

IEEE Transactions on Electron Devices

Volumn 53, Issue 4, 2006, Pages 698-705

  Kumar, P Bharath ^a   Nair, Pradeep R ^a,b   Sharma, Ravinder ^a,c   Kamohara, Shiro ^d   Mahapatra, Souvik ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b PURDUE UNIVERSITY   (United States)

^c STMICROELECTRONICS   (Italy)

^d RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Channel hot electron (CHE) injection; Charge pumping (CP); Gate induced drain leakage (GIDL); Nonuniform charge trapping; Silicon oxide silicon (SONOS) electrically erasable programmable read only memories (EEPROMs); Trapped charge profiling

Indexed keywords

COMPUTER SIMULATION; FLASH MEMORY; ITERATIVE METHODS; MONTE CARLO METHODS; SEMICONDUCTING SILICON; THRESHOLD VOLTAGE;

CHANNEL HOT ELECTRON (CHE) INJECTION; CHARGE PUMPING (CP); GATE INDUCED DRAIN LEAKAGE (GIDL); NONUNIFORM CHARGE TRAPPING; SILICON OXIDE SILICON (SONOS); TRAPPED CHARGE PROFILING;

PROM;

EID: 33645728372     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.870533     Document Type: Article

References (20)

1. P. R. Nair, P. B. Kumar, R. Sharma, S. Kamohara, and S. Mahapatra, "A comprehensive trapped charge profiling technique for SONOS flash EEPROMs," in IEDM Tech. Dig., 2004, pp. 403-406.
2. T. Y. Chan, K. K. Young, and C. Hu, "A true single-transistor oxidenitride-oxide EEPROM device," IEEE Electron Device Lett., vol. EDL-8, no. 3, pp. 93-95, Mar. 1987.
3. M. H. White, Y. L. Yang, A. Purwar, and M. L. French, "A low voltage SONOS nonvolatile semiconductor memory technology," IEEE Trans. Compon., Packag., Manuf. Technol. A, vol. 20, no. 2, pp. 190-195, Jun. 1997.
4. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "Can NROM, a 2-bit, trapping storage NVM cell, give a real challenge to floating gate cells?," in Proc. SSDM, 1999, pp. 522-524.
5. E. J. Prinz, G. L. Chindalore, K. Harber, C. M. Hong, C. B. Li, and C. T. Swift, "An embedded 90 nm SONOS flash EEPROM utilizing hot electron injection programming and 2-sided hot hole injection erase," in Proc. IEEE NVSMW, 2003, pp. 56-57.
6. G. Xue, J. Van Houdt, D. Wellekens, L. Haspeslagh, P. Hedrickx, J. De Vos, and H. E. Maes, "Low voltage low cost nitride embedded flash memory cell," in Proc. IEEE NVSMW, 2003, pp. 62-64.
7. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 42-53, Jan. 1984.
8. M. Tsuchiaki, H. Hara, T. Morimoto, and H. Iwai, "A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFETs," IEEE Trans. Electron Devices, vol. 40, no. 10, pp. 1768-1779, Oct. 1993.
9. W. K. Chim, S. E. Leang, and D. S. H. Chan, "Extraction of metal-oxide-semiconductor field-effect-transistor interface state and trapped charge spatial distributions using a physics-based algorithm," J. Appl. Phys., vol. 81, no. 4, pp. 1992-2001, Feb. 1997.
10. S. Mahapatra, C. D. Parikh, J. Vasi, V. R. Rao, and C. R. Viswanathan, "Direct charge pumping technique for spatial profiling of hot-carrier-induced interface and oxide traps MOSFETs," Solid State Electron., vol. 43, no. 5, pp. 915-922, May 1999.
11. Y. L. Chu, D. W. Lin, and C. Y. Wu, "A new charge-pumping technique for profiling the interface-states and oxide-trapped charges in MOSFETs," IEEE Trans. Electron Devices, vol. 47, no. 2, pp. 348-353, Feb. 2000.
12. A. M. Martirosian and T. P. Ma, "Improved charge-pumping method for lateral profiling of interface traps and oxide charge in MOSFET devices," IEEE Trans. Electron Devices, vol. 48, no. 10, pp. 2303-2309, Oct. 2001.
13. M. Rosmeulen, L. Breuil, M. Lorenzini, L. Haspeslagh, J. Van Houdt, and K. De Meyer, "Characterization of the spatial charge distribution in local charge-trapping memory devices using the charge-pumping technique," Solid State Electron., vol. 48, no. 9, pp. 1525-1530, 2004.
14. E. Lusky, Y. Shacham-Diamand, G. Mitenberg, A. Shappir, I. Bloom, and B. Eitan, "Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices," IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 444-451, Mar. 2004.
15. ISE TCAD Manuals, Release 8.0, Zurich, Switzerland: Synopsys, Inc. Online. Available: www.ise.ch
16. J. D. Bude, M. R. Pinto, and R. K. Smith, "Monte Carlo simulation of CHISEL flash memory cell," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1873-1881, Oct. 2000.
17. L. Larcher, G. Verzellesi, P. Pavan, E. Lusky, I. Bloom, and B. Eitan, "Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1939-1946, Nov. 2002.
18. Y. Roizin, M. Gutman, S. Alfassi, and R. Yosefi, "In-process charging in MicroFLASH memory cells," in Proc. IEEE NVSMW, 2003, pp. 83-84.
19. C. Chang and J. Lien, "Corner-field induced drain leakage in thin oxide MOSFETs," in IEDM Tech. Dig., 1987, pp. 714-717.
20. T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, "The impact of gate-induced drain leakage current on MOSFET scaling," in IEDM Tech. Dig., 1987, pp. 718-721.