A dynamical power-management demonstration using four-terminal separated-ate FinFETs

IEEE Electron Device Letters

Volumn 28, Issue 5, 2007, Pages 452-454

  Endo, K ^a   Ishikawa, Y ^a   Liu, Y X ^a   Matsukawa, T ^a   O'uchi, S ^a   Ishii, K ^a   Masahara, M ^a   Tsukada, J ^a   Yamauchi, H ^a   Sekigawa, T ^a   Koike, H ^a   Suzuki, E ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

CMOS inverter; Etch back; FinFET; Four terminal (4T); Power management; Vth

Indexed keywords

BIAS VOLTAGE; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; GATE DIELECTRICS; POWER CONTROL; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

CMOS INVERTERS; CONTROL GATE; POWER MANAGEMENT;

FIELD EFFECT TRANSISTORS;

EID: 34247620865     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.895451     Document Type: Article

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