Power-aware 65 nm node CMOS technology using variable VDD and back-bias control with reliability consideration for back-bias mode

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 88-89

  Togo, M ^a   Fukai, T ^a   Nakahara, Y ^b   Koyama, S ^c   Makabe, M ^c   Hasegawa, E ^c   Nagase, M ^c   Matsuda, T ^c   Sakamoto, K ^c   Fujiwara, S ^c   Goto, Y ^b   Yamamoto, T ^a   Mogami, T ^a   Ikeda, M ^b   Yamagata, Y ^b   Imai, K ^b  

^a NEC CORPORATION   (Japan)

^b Advanced Device Development Division   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; LITHOGRAPHY; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MOS CAPACITORS; THRESHOLD VOLTAGE;

ACTIVE POWER REDUCTION; BACK-BIAS MODE; INVERTER GATES; POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS;

EID: 4544300030     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. Y. Mitani et al., IEDM Tech. Dig., p. 509, 2002.
3. N. Kimizuka et al., Symp. VLSI Tech., p.92, 2000.
4. S. Tsujikawa et al., Symp. VLSI Tech., p. 139, 2003.
5. K. Jeppson et al., JAP, Vol. 48, p.2004, 1977.