Comparison of the work function of Pt-Ru binary metal alloys extracted from MOS capacitor and Schottky-barrier-diode measurements

IEEE Transactions on Electron Devices

Volumn 54, Issue 4, 2007, Pages 807-813

  Todi, Ravi M ^a   Erickson, Matthew S ^a   Sundaram, Kalpathy B ^a   Barmak, Katayun ^b   Coffey, Kevin R ^a  

^a UNIVERSITY OF CENTRAL FLORIDA   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Gate electrode; Metal alloy; Pt Ru; Schottky; Work function

Indexed keywords

CAPACITANCE; CRYSTAL STRUCTURE; ELECTRIC CONDUCTIVITY; ELECTRIC POTENTIAL; MOS CAPACITORS; PHASE DIAGRAMS; SCHOTTKY BARRIER DIODES; WORK FUNCTION;

FACE-CENTERED CUBIC; GATE ELECTRODE;

BINARY ALLOYS;

EID: 34147156194     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.892352     Document Type: Article

References (19)

1. H. Zhong, S.-N. Hong, Y.-S. Suh, H. Lazar, G. Heuss, and V. Misra, "Properties of Ru-Ta alloys as gate electrodes for nMOS and pMOS silicon devices, in IEDM Tech. Dig., 2001, pp. 467-470.
2. V. Misra, H. Zhong, and H. Lazar, "Electrical properties of Ru-based alloy gate electrodes for dual gate Si-CMOS," IEEE Electron Device Lett., vol. 23, no. 6, pp. 354-356, Jun. 2002.
3. P. Majhi, C. Young, G. Bersuker, H.-C. Wang, A. Brown, B. Foran, R. Choi, P. M. Zeitzoff, and H. R. Huff, "Influence of metal gate materials and processing on planar CMOS device characteristics with high-Κ, gate dielectric," in Proc. 34th Eur. Solid State Device Res. Conf., 2004, pp. 185-188.
4. C. Cabral, Jr., C. Lavoie, A. S. Ozcan, R. S. Amos, V. Narayanan, E. P. Gusev, J. L. Jordan-Sweet, and J. M. E. Harper, "Evaluation of thermal stability for CMOS gate metal materials," J. Electrochem. Soc., vol. 151, no. 12, pp. F283-F287, 2004.
5. 2 gate dielectrics," Appl. Phys. Lett., vol. 81, no. 7, pp. 1288-1290, Aug. 2002.
6. 2 and Zr silicate gate dielectrics," in IEDM Tech. Dig., 2000, pp. 27-30.
7. E. Cartier, V. Narayanan, E. P. Gusev, P. Jamison, B. Linder, M. Steen, K. K. Chan, M. Frank, N. Bojarczuk, M. Copel, S. A. Cohen, S. Zafar, A. Callegarir, M. Gribelyuk, M. P. Chudzik, C. Cabral, Jr., R. Carruthers, C. D'Emic, J. Newbury, D. Lacey, S. Guha, and R. Jammy, "Systematic study of pFET Vt with Hf-based gate stacks with poly-Si and FUSI gates," in VLSI Symp. Tech. Dig., 2004, pp. 44-45.
8. R. Lin, Q. Lu, P. Ranade, T.-J. King, and C. Hu, "An adjustable workfunction technology using Mo gate for CMOS devices," IEEE Electron Device Lett., vol. 23, no. 1, pp. 49-51, Jan. 2002.
9. C. Cabral, Jr., J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carruthers, and R. Jammy, "Dual work function fully silicide metal gates," in VLSI Symp. Tech. Dig., Jun. 2004, pp. 15-17.
10. H. Zhong, S.-N. Hong, Y.-S. Suh, H. Lazar, G. Heuss, and V. Misra, "Properties of Ru-Ta alloys as gate electrodes for nMOS and pMOS silicon devices," in IEDM Tech. Dig., 2001, pp. 467-470.
11. W. Gao, J. F. Conley, and Y. Ono, "Stack metal layers as gates for MOSFET threshold voltage control," in Proc. Mater. Rec. Soc. Symp. 2003, vol. 765, pp. D1.4-D1.6.
12. J. S. Jeon, J. Lee, P. Zhao, P. Sivasubramani, T. Oh, H. J. Kim, D. Cha, J. Huang, M. J. Kim, B. E. Gnade, J. Kim, and R. M. Wallace, "A novel methodology on tuning work function of metal gate using stacking bilayers," in IEDM Tech. Dig., 2004, pp. 303-306.
13. B. Cheng, B. Maiti, S. B. Samavedam, J. Grant, B. Taylor, P. Tobin, and J. Mogab, "Metal gates for advanced sub-80-nm SOI CMOS technology," in Proc. IEEE Int. SOI Symp., 2001, pp. 91-92.
14. Z. B. Zhang, S. C. Song, C. Huffman, J. Barnett, H. Alshareef, P. Majhi, M. Hussain, M. S. Akbar, J. H. Sim, S. H. Bae, B. Sassman, and B. H. Lee, "Integration of dual metal gate CMOS with TaSiN (nMOS) and Ru(pMOS) gate electrodes on HfO2 gate dielectric," in VLSI Symp. Tech. Dig., 2005, pp. 50-51.
15. R. M. Todi, A. P. Warren, K. B. Sundaram, K. Barmak, and K. R. Coffey, "Characterization of Pt-Ru alloys thin films for work function tuning," IEEE Elec. Dev. Let., vol. 27, no. 7, pp. 542-545, Jul. 2006.
16. D. K. Schroder, Semiconductor Materials and Device Characterization 3rd ed. Hoboken, NJ: Wiley, 2006.
17. G. Myburg, F. D. Auret, W. E. Meyer, C. W. Louw, and M. J. Van Staden, "Summary of Schottky barrier height data on epitaxially grown n- and p-GaAs," Thin Solid Films, vol. 325, no. 1/2, pp. 181-186, Jul. 1998.
18. J. R. Hauser and K. Ahmed, "Characterization of ultrathin oxides using electrical C-V and I-V measurements," in Proc. AIP. Conf., 1998, pp. 235-239.
19. T. B. Massalski, Ed., Binary Alloy Phase Diagrams, 2nd ed. Materials Park, OH: ASM Int., 1990.