A novel methodology on tuning work function of metal gate using stacking Bi-metal layers

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 303-306

  Jeon, I S ^a,c   Lee, J ^b   Zhao, P ^a   Sivasubramani, P ^a   Oh, T ^b   Kim, H J ^c   Cha, D ^a   Huang, J ^a   Kim, M J ^a   Gnade, B E ^a   Kim, J ^a,b   Wallace, R M ^a  

^a The University of Texas at Dallas   (United States)

^b Kookmin University   (South Korea)

^c Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; DIELECTRIC DEVICES; ELECTRIC POTENTIAL; EVAPORATION; HIGH RESOLUTION ELECTRON MICROSCOPY; POLYSILICON; RUTHERFORD BACKSCATTERING SPECTROSCOPY; SEMICONDUCTOR JUNCTIONS; SPUTTERING; TRANSMISSION ELECTRON MICROSCOPY; CARRIER CONCENTRATION; ELECTRON DENSITY MEASUREMENT; GATE DIELECTRICS; METALS; MOS DEVICES; OXIDE SEMICONDUCTORS; TUNING;

BILAYER METAL GATE ELECTRODES; FLAT BAND VOLTAGE; INTERFACIAL ALLOYING; METAL GATES;

GATES (TRANSISTOR); WORK FUNCTION;

BULK METALS; CAPACITOR STRUCTURES; FLAT-BAND VOLTAGE; METAL LAYER; METAL-GATE; METALS A; NOVEL METHODOLOGY; STACKINGS; THIN LAYERS; THIN METAL LAYERS;

EID: 21644448985     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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