A simple model for threshold voltage of surrounding-gate MOSFET's

IEEE Transactions on Electron Devices

Volumn 45, Issue 11, 1998, Pages 2381-2383

  Auth, Christopher P ^a,b   Plummer, James D ^a  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

MOSFET; Silicon

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; MATHEMATICAL MODELS; THRESHOLD VOLTAGE;

DRAIN-INDUCED BARRIERS; SHORT CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0032205525     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.726665     Document Type: Article

References (9)

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2. H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, "Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's," IEEE Trans. Electron Devices, vol. 38, pp. 573-578, Mar. 1991.
3. C. Auth and J. Plummer, "Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's," IEEE Electron Device Lett., vol. 18, pp. 74-76, Feb. 1997.
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7. C. Auth, "Physics and technology of vertical surrounding gate MOSFET's," Ph.D. dissertation, Stanford Univ., Stanford, CA, Feb. 1998.
8. + double-gate SOI MOSFET's," IEEE Trans. Electron Devices, vol. 43, pp. 732-738, May 1996.
9. S.-S. Chen and J. B. Kuo, "Deep submicrometer double-gate fully-depleted SOI PMOS devices: A concise short-channel effect threshold voltage model using quasi-2D approach," IEEE Trans. Electron Devices, vol. 43, pp. 1387-1393, Sept. 1996.