High performance III/V RTD and PIN diode on a silicon (001) substrate

Applied Physics A: Materials Science and Processing

Volumn 87, Issue 3, 2007, Pages 539-544

  Prost, W ^a   Khorenko, V ^a,b   Mofor, A C ^a,c   Neumann, S ^a   Poloczek, A ^a   Matiss, A ^a   Bakin, A ^c   Schlachetzki, A ^c   Tegude, F J ^a  

^a UNIVERSITY OF DUISBURG ESSEN   (Germany)

^b AZUR SPACE Solar Power GmbH   (Germany)

^c TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

OPTOELECTRONIC DEVICES; RESONANT TUNNELING; SEMICONDUCTING SILICON; SEMICONDUCTOR GROWTH; SEMICONDUCTOR SUPERLATTICES;

DEVICE MODELS; OPTICAL RECEIVER CIRCUITS; RESONANT TUNNELLING DIODES; SILICON SUBSTRATES;

DIODES;

EID: 33947267488     PISSN: 09478396     EISSN: 14320630     Source Type: Journal    
DOI: 10.1007/s00339-007-3920-1     Document Type: Article

References (31)

1. M. Kai, R. Urata, D. A. B Miller, J.S. Harria, IEEE J. Quantum Electron. QE-40, 800 (2004)
2. Y.T. Sun, J. Napierala, S. Lourdudoss, Selective area growth of InP on InP precoated silicon substrate by hydride vapor phase epitaxy, IEEE Proc. 14th Indium Phosphide and Related Materials Conference, Sweden, 12-16 May 2002, pp. 339-342
3. D.J. Paul, Semicond. Sci. Technol. 19, R75 (2004) PII: S0268-1242(04)61523-9
4. J.D. Schaub, SJ. Koester, G. Dehlinger, Q.C. Ouyang, D. Guckenberger, Y. Min, D.L. Rogers, J. Chu, A. Grill, High-speed lateral PIN photodiodes in silicon technologies, Proc. Int. Soc. Opt. Eng., USA, Vol. 5353 (2004), pp. 1-11
5. S.C. Tan, Y.C. Chan, N.S.M. Lui, IEEE Trans. Adv. Packaging 29, 570 (2006)
6. U. Gosele, III-V materials integration technologies: wafer bonding approaches, IEEE Proc. Int. Conf. Indium Phosphide and Related Materials, Williamsburg, 14-18 May 2000, pp. 9-12
7. T. Nakahara, H. Tsuda, N. Ishihara, K. Tateno, C. Amano, Electron. Lett. 37, 781 (2001)
8. J.P. Van der Ziel, R.D. Dupuis, R.A. Logan, C. Pinzone, Appl. Phys. Lett. 51, 89 (1987)
9. T. Sasaki, H. Mori, M. Tachikawa, T. Yamada, J. Appl. Phys. 84, 6725 (1998)
10. B. Gerard, X. Marcadet, P. Etienne, D. Pribat, J. Nagle, F. Carlin, M. Ilegems, D. Friedrich, J. Eichholz, H. Bernt, MRS Symp. Proc. Ser. 533, FF4.2 (1998)
11. K. Linthicum, T. Gehrke, D. Thomson, E. Carlson, P. Rajoagopal, T. Smith, D. Batchelor, R. Davis, Appl. Phys. Lett. 75, 196 (1999)
12. M. Sugo, H. Mori, Y. Sakai, Y. Itoh, Appl. Phys. Lett. 60, 472 (1992)
13. R.D. Bringans, D.K. Biegelsen, L.-E. Swartz, Phys. Rev. B 44, 3054 (1991)
14. O. Parillaud, E. Gil-Lafon, B. Gerard, P. Etienne, D. Pribat, Phys. Lett. 68, 2654 (1996)
15. D. Zubia, S.D. Hersee, J. Appl. Phys. 85, 6492 (1999)
16. A. Bakin, D. Piester, I. Behrens, H.-H. Wehmann, E. Peiner, A. Ivanov, D. Fehly, A. Schlaschetzki, Growth of InP Layers on Nanometer-Scale Patterned Si Substrate, in: Crystal Growth and Design (2003), vol. 3, pp. 89-93
17. S. Neumann, A. Bakin, W. Prost, H.-H. Wehmann, A. Schlachetzki, F.-J. Tegude, J. Cryst. Growth 248, 380 (2003)
18. V. Khorenko, A.-C. Motor, A. Bakin, S. Neumann, A. Guttzeit, H.H. Wehmann, W. Prost, A. Schlachetzki, F.J. Tegude, Buffer Optimization for InP-on-Si(001) Quasi-Substrates, 16th InP & Related Materials Conference, Kagoshima City, Japan, May 31 to June 4, (2004)
19. P. Veiling, M. Agethen, W. Prost, F.J. Tegude, J. Cryst. Growth 221, 722 (2000)
20. K. Asai, K. Fujita, Y. Shiba, Japan. J. Appl. Phys. 60, L1967 (1991)
21. K. Samonji, H. Yonezu, Y. Takagi, K. Iwaki, N. Ohshima, J.K. Shin, K. Pak, Appl. Phys. Lett. 69, 100 (1996)
22. J.W. Mattews, A.E. Blakeslee, J. Cryst. Growth 27, 118 (1974)
23. D.C. Houghton, M. Davies, M. Dion, Appl. Phys. Lett. 64, 505 (1994)
24. G.W. Pickell, K.L. Chang, J.H. Epple, K.Y. Cheng, K.C. Hsieh, J. Vac. Sci. Technol. B 18, 2611 (2000)
25. S. Muto, T. Inata, Semicond. Sci. Technol. 9, 1157 (1994)
26. C. Pacha, U. Auer, C. Burwick, P. Glösekötter, A. Brennemann, W. Prost, F.J. Tegude, K.F. Goser, Threshold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices, IEEE Transactions on Very Large Scale Integration Systems, Vol. 8 (2000), pp. 558-572
27. D. Fehly, A. Schlachetzki, A. Bakin, A. Guttzeit, H.-H. Wehmann, J. Quantum Electron. QE-37, 1246 (2001)
28. A. Poloczek, A. Stöhr, W. Prost, L Regolin, D. Jäger, F.-J. Tegude, High Performance III/V PIN-Diode on a Silicon(001) Substrate for Optoelectronic Receivers, 2006 European ISIS Workshop, Boppard am Rhein, Germany, May 29 (2006)
29. K. Sano, K. Murata, T. Otsuji, T. Akeyoshi, N. Shimizu, E. Sano, IEEE J. Sol. State Circuits 36, 281 (2001)
30. Z. Yan, M.J. Deen, IEEE Trans. Computer-Aided Design Int. Circuits Systems 2, 167 (1995)
31. Final Report Quantum Tunneling Device Technology on Silicon, QUDOS, IST-2001-32358