Opens and delay faults in CMOS RAM address decoders

IEEE Transactions on Computers

Volumn 55, Issue 12, 2006, Pages 1630-1639

  Hamdioui, Said ^a,b   Al Ars, Zaid ^a,b   Van De Goor, Ad J ^a,b  

^a IEEE   (Netherlands)

^b Department of Microelectronics   (Netherlands)

Author keywords

Address decoder delay faults; Addressing methods; BIST; DFT; Memory testing; Open defects

Indexed keywords

ADDRESS DECODER DELAY FAULTS; ADDRESSING METHODS; MEMORY TESTING; OPEN DEFECTS;

CLASSIFICATION (OF INFORMATION); CMOS INTEGRATED CIRCUITS; DECODING; DENSITY FUNCTIONAL THEORY;

RANDOM ACCESS STORAGE;

EID: 33947241222     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2006.203     Document Type: Article

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