Open defects in CMOS RAM address decoders

IEEE Design and Test of Computers

Volumn 14, Issue 2, 1997, Pages 26-33

  Sachdev, Manoj ^a,b,c,d,e  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b Philips Research Laboratories ^*  (India)

^c STMICROELECTRONICS   (Italy)

^d INDIAN INSTITUTE OF TECHNOLOGY ROORKEE   (India)

^e BRUNEL UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER TESTING; DECODING; DEFECTS; ERROR DETECTION; FAILURE ANALYSIS; LOGIC GATES; PERFORMANCE;

DECODERS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; OPEN DEFECTS;

RANDOM ACCESS STORAGE;

EID: 0031123487     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.587738     Document Type: Article

References (12)

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