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Volumn 2003-January, Issue , 2003, Pages 250-255

Comparison of open and resistive-open defect test conditions in SRAM address decoders

Author keywords

[No Author keywords available]

Indexed keywords

DECODING;

EID: 3142748931     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250818     Document Type: Conference Paper
Times cited : (17)

References (13)
  • 4
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    • Marinescu, M.1
  • 5
    • 0033750078 scopus 로고    scopus 로고
    • Functional Memory Faults: A Formal Notation and a Taxonomy
    • May
    • A.J. van de Goor and Z. Al-Ars, "Functional Memory Faults: A Formal Notation and a Taxonomy", Proc. IEEE VLSI Test Symposium, May 2000, pp.281-289.
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    • Van De Goor, A.J.1    Al-Ars, Z.2
  • 6
    • 84893689177 scopus 로고    scopus 로고
    • Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs
    • Z. Al-Ars and A.J. van de Goor, "Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs", Proc. Design, Automation and Test in Europe, 2001, pp. 496-503.
    • (2001) Proc. Design, Automation and Test in Europe , pp. 496-503
    • Al-Ars, Z.1    Van De Goor, A.J.2
  • 7
    • 0029735629 scopus 로고    scopus 로고
    • Test and Testability Techniques for Open Defects in RAM Address Decoders
    • M. Sachdev, "Test and Testability Techniques for Open Defects in RAM Address Decoders", Proc. IEEE European Design & Test Conference, 1996, pp.428-434.
    • (1996) Proc. IEEE European Design & Test Conference , pp. 428-434
    • Sachdev, M.1
  • 8
    • 0031123487 scopus 로고    scopus 로고
    • Open Defects in CMOS RAM Address Decoders
    • Apr-Jun
    • M. Sachdev, "Open Defects in CMOS RAM Address Decoders", IEEE Design & Test of Computers, vol.14, n.2, Apr-Jun 1997, pp. 26-33.
    • (1997) IEEE Design & Test of Computers , vol.14 , Issue.2 , pp. 26-33
    • Sachdev, M.1
  • 9
    • 0032312595 scopus 로고    scopus 로고
    • Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests
    • J. Otterstedt, D. Niggemeyer and T.W. Williams, "Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests", Proc. Int. Test Conf., 1998, pp.53-62.
    • (1998) Proc. Int. Test Conf. , pp. 53-62
    • Otterstedt, J.1    Niggemeyer, D.2    Williams, T.W.3
  • 10
    • 0035701578 scopus 로고    scopus 로고
    • A Microcode-based Memory BIST Implementing Modified March Algorithm
    • D. Youn, T. Kim and S. Park, "A Microcode-based Memory BIST Implementing Modified March Algorithm", Proc. of Asian Test Symposium, 2001, pp. 391-395.
    • (2001) Proc. of Asian Test Symposium , pp. 391-395
    • Youn, D.1    Kim, T.2    Park, S.3
  • 12
    • 0036732498 scopus 로고    scopus 로고
    • Resistance Characterization of Interconnect Weak and Strong Open Defects
    • Sept-Oct
    • R. Rodriquez Montanés, P. Volf and J. Pineda de Gyvez, "Resistance Characterization of Interconnect Weak and Strong Open Defects", IEEE Design & Test of Computers, vol.19, n.5, Sept-Oct 2002, pp.18-26.
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  • 13
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    • Test for resistive and capacitive defects in address decoders
    • M. Klaus and Ad J. van de Goor "Test for resistive and capacitive defects in address decoders", Proc. of Asian Test Symposium, 2001, pp. 31-36.
    • (2001) Proc. of Asian Test Symposium , pp. 31-36
    • Klaus, M.1    Van De Goor, A.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.