Detection of delay faults in memory address decoders

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 4, 2000, Pages 381-387

  Gizdarski, Emil ^a,b  

^a UNIVERSITY OF RUSE   (Bulgaria)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); COMPUTER SIMULATION; DECODING; DESIGN FOR TESTABILITY; NAND CIRCUITS; RANDOM ACCESS STORAGE;

DELAY FAULTS DETECTION; GRAY CODE; HAYES TRANSFORMATION; MEMORY ADDRESS DECODERS; STUCK OPEN FAULTS; TRANSITION SEQUENCE GENERATOR;

DELAY CIRCUITS;

EID: 0034249321     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008322103755     Document Type: Article

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