A low energy encoding technique for reduction of coupling effects in SoC interconnects

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages 80-83

  Baek, Kwang Hyun ^a   Kim, Ki Wook ^a   Kang, Sung Mo ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; SIGNAL ENCODING;

COUPLING EFFECTS; LOW ENERGY SET SCHEME; SILICON ON CHIP INTERCONNECTS; SLIM ENCODING STRUCTURE;

MICROPROCESSOR CHIPS;

EID: 0034464156     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Bus-invert coding for low-power I/O
2. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
3. Exploiting the locality of memory references to reduce the address bus energy
4. Some issues in gray code addressing
5. Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
6. Two-dimensional codes for low-power
7. Conditional capture flip-flop technique for statistical power reduction
8. Low-power digital design