Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 194-199

  Kaul, Himanshu ^a   Sylvester, Dennis ^a   Anders, Mark ^b   Krishnamurthy, Ram ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Design; Performance

Indexed keywords

BUSES; DATA COMMUNICATION SYSTEMS; ELECTRIC CURRENTS; FORMAL LOGIC; INPUT OUTPUT PROGRAMS; INTERFACES (COMPUTER); OPTIMIZATION; PERFORMANCE;

ENERGY GAINS; HIGH-PERFORMANCE BUSES; POWER REDUCTION; SPATIAL ENCODER CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 16244375549     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013286     Document Type: Conference Paper

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