CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 198-199

  Anil, K G ^a   Verheyen, P ^a   Collaert, N ^a   Dixit, A ^a,b   Kaczer, B ^a   Snow, J ^a   Vos, R ^a   Locorotondo, S ^a   Degroote, B ^a   Shi, X ^a   Rooyackers, R ^a   Mannaert, G ^a   Brus, S ^a   Yim, Y S ^c   Lauwers, A ^a   Goodwin, M ^d   Kittl, J A ^d   Van Dal, M ^e   Richard, O ^a   Veloso, A ^a   Kubicek, S ^a   Beckx, S ^a   Boullart, W ^a   De Meyer, K ^a,b   Absil, P ^a   Jurczak, M ^a   Biesemans, S ^a   more..

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c SAMSUNG Electronics   (South Korea)

^d TEXAS INSTRUMENTS   (United States)

^e PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMP-LESS INTEGRATION; GATE LENGTH; NI-SILICIDED METAL GATES; SILICIDATION;

CHEMICAL MECHANICAL POLISHING; FIELD EFFECT TRANSISTORS; MASKS; NICKEL COMPOUNDS; REACTION KINETICS; VOLATILE ORGANIC COMPOUNDS;

GATES (TRANSISTOR);

EID: 33645699787     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469266     Document Type: Conference Paper

References (7)

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5. J. Kedzierski., IEDM Tech. Dig., 2002, p. 247.
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7. IEDM 2004, papers in session 4, Process Technology: Fully-silicided (FUSI) gates, Tech. Dig. p. 77-102.