Protecting combinational logic synthesis solutions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 12, 2006, Pages 2687-2696

  Kirovski, Darko ^a,b   Hwang, Yean Yow ^c   Potkonjak, Miodrag ^a,d   Cong, Jason ^d  

^a IEEE   (United States)

^b MICROSOFT RESEARCH   (United States)

^c Velogix Inc   (United States)

^d University of California   (United States)

Author keywords

Intellectual property protection; Logic synthesis; Multilevel combinational synthesis; Template matching; Water marking

Indexed keywords

INTELLECTUAL PROPERTY PROTECTION; LOGIC SYNTHESIS; MULTILEVEL COMBINATIONAL SYNTHESIS; TEMPLATE MATCHING;

COPYRIGHTS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PATTERN MATCHING; PROBABILITY; WATERMARKING;

COMBINATORIAL CIRCUITS;

EID: 33845622506     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.882490     Document Type: Article

References (37)

1. L. Babel et al., "Directed path graph isomorphism," in Proc. Int. Workshop Graph-Theoretic Concepts Comput. Sci., 1995, pp. 395-400.
2. V. Bertacco and M. Damiani, "The disjunctive decomposition of logic functions," in Proc. ICCAD, 1997, pp. 78-82.
3. R. K. Brayton et al., "MIS: A multiple-level logic optimization system," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. CAD-6, no. 6, pp. 1062-1081, Nov. 1987.
4. A. E. Caldwell et al., "Effective iterative techniques for fingerprinting design IP," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 2, pp. 208-215, Feb. 2004.
5. R. Chapman and T. Durrani, "IP protection of DSP algorithms for system on chip implementation," IEEE Trans. Signal Process., vol. 48, no. 3, pp. 854-861, Mar. 2000.
6. E. Charbon, "Hierarchical watermarking in IC design," in Proc. CICC, 1998, pp. 295-305.
7. E. Charbon and I. Torunoglu, "Watermarking layout topologies," in Proc. ASP-DAC, 1999, vol. 1, pp. 213-216.
8. D. Chen and J. Cong, "DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs," in Proc. ICCAD, 2004, pp. 752-757.
9. J. Cong and C. Wu, "An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design," in Proc. ICCAD, 1996, pp. 572-578.
10. J. Cong and Y. Ding, "Combinational logic synthesis for LUT based field programmable gate arrays," ACM Trans. Design Automat. Electron. Syst., vol. 1, no. 2, pp. 145-204, 1996.
11. J. Cong and Y.-Y. Hwang, "Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 9, pp. 1077-1090, Sep. 2001.
12. J. Cong and Y. Ding, "On nominal delay minimization in LUT-based FPGA technology mapping," in Proc. FPGA, 1995, pp. 82-88.
13. G. Chen and J. Cong, "Simultaneous logic decomposition with technology mapping in FPGA designs," in Proc. FPGA, 2001, pp. 48-55.
14. G. De Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
15. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. New York: Freeman, 1979.
16. G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms. Boston, MA: Kluwer, 1996.
17. I. Hong and M. Potkonjak, "Techniques for intellectual property protection of DSP designs," in Proc. IEEE ICASSP, 1998, pp. 3133-3136.
18. J.-D. Huang et al., "An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping," in Proc. ICCAD, 1996, pp. 13-17.
19. D. Irby et al., "Low level watermarking of VLSI designs for intellectual property protection," in Proc. Int. Conf. ASIC/SOC, 2000, pp. 136-140.
20. A. B. Kahng et al., "Robust intellectual property watermarking methodologies for physical design," in Proc. DAC, 1998.
21. _, "Constraint-based watermarking techniques for design IP protection," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 10, pp. 1236-1252, Oct. 2001.
22. D. Kirovski and M. Potkonjak, "Local watermarks: Methodology and application to behavioral synthesis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 9, pp. 1277-1284, Sep. 2003.
23. D. Kirovski et al., "Intellectual property protection by watermarking combinational logic synthesis solutions," in Proc. ICCAD, 1998, pp. 194-198.
24. F. Koushanfar et al., "Behavioral synthesis techniques for intellectual property protection," ACM TODAES, vol. 10, no. 3, pp. 523-545, Jul. 2005.
25. J. Lach et al., "Fingerprinting digital circuits on programmable hardware," in Proc. Inf. Hiding Workshop, 1998, pp. 16-31.
26. _, "Fingerprinting techniques for field programmable gate array intellectual property protection," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 10, pp. 1253-1261, Oct. 2001.
27. S. Liao and S. Devadas, "Solving covering problems using LPR-based lower bounds," in Proc. DAC, 1997, pp. 117-120.
28. S. Meguerdichian and M. Potkonjak, "Watermarking while preserving the critical path," in Proc. DAC, 2000, pp. 108-111.
29. A. J. Menezes et al., Handbook of Applied Cryptography. Boca Raton, FL: CRC, 1997.
30. A. Mishchenko et al., "Improvements to technology mapping for LUT-based FPGAs," in Proc. Int. Symp. FPGAs, 2006, pp. 41-49.
31. R. Newbould et al., "Watermarking ICs for IP protection," Electron. Lett., vol. 38, no. 6, pp. 272-274, Mar. 2002.
32. A. Oliveira, "Techniques for the creation of digital watermarks in sequential circuit designs," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 9, pp. 1101-1117, Sep. 2001.
33. A. Rashid et al., "Hierarchical watermarking for protection of DSP filter cores," in Proc. CICC, 1999, pp. 39-42.
34. G. Wolfe et al., "Watermarking graph partitioning solutions," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 10, pp. 1196-1204, Oct. 2002.
35. J. L. Wong et al., "Optimization-intensive watermarking techniques for decision problems," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 1, pp. 119-127, Jan. 2004.
36. _, "Computational forensic techniques for intellectual property protection," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 6, pp. 987-994, Jun. 2004.
37. _, "Fair watermarking using combinatorial isolation lemmas," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 11, pp. 1566-1574, Nov. 2004.