Iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 13-17

  Huang, Juinn Dar ^a   Jou, Jing Yang ^a   Shen, Wen Zen ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK SYNTHESIS; ITERATIVE METHODS; OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); TECHNOLOGY MAPPING;

LOGIC GATES;

EID: 0030408903     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)