Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 9, 2001, Pages 1077-1090

  Cong, Jason ^a,b   Hwang, Yean Yow ^c  

^a IEEE   (United States)

^b University of California   (United States)

^c ALTERA CORPORATION   (United States)

Author keywords

FPGA architecture; Logic synthesis

Indexed keywords

BOOLEAN MATCHING; LOGIC BLOCKS;

ALGORITHMS; BLOCK CODES; BOOLEAN ALGEBRA; FUNCTION EVALUATION; LOGIC DESIGN; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035440923     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.945303     Document Type: Article

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