Soft error mitigation for SRAM-based FPGAs

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 207-212

  Asadi, Ghazanfar Hossein ^a   Tahoori, Mehdi Baradaran ^a  

^a Northeastern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC DESIGN; MITIGATION TECHNIQUES; ORDERS OF MAGNITUDE; PERMANENT ERRORS; SINGLE EVENT UPSETS; SOFT ERROR MITIGATIONS;

COMPUTER CONTROL SYSTEMS; DESIGN; INTEGRATED CIRCUITS;

AVAILABILITY;

EID: 33845594463     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.75     Document Type: Conference Paper

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