Implementing register files for high-performance microprocessors in a die-stacked (3D) technology

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

Volumn 2006, Issue , 2006, Pages 384-389

  Puttaswamy, Kiran ^a   Loh, Gabriel H ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Georgia Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIE STACKED (3D) TECHNOLOGY; ENERGY REDUCTION; REGISTER FILES; WIRE DOMINATED CIRCUITS;

BANDWIDTH; CACHE MEMORY; ENERGY UTILIZATION; FILE ORGANIZATION; INTEGRATED CIRCUITS; INTERFACES (COMPUTER); NETWORKS (CIRCUITS);

MICROPROCESSOR CHIPS;

EID: 33749333423     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2006.56     Document Type: Conference Paper

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