Towards formal probabilistic power-performance design space exploration

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 229-234

  Kim, Joonsoo ^a   Orshansky, Michael ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Canonical representation; Formal methodology; Hierarchical design exploration; Performance; Power; Probabilistic

Indexed keywords

DESIGN FOR TESTABILITY; HIERARCHICAL SYSTEMS; NUMERICAL METHODS; PARALLEL ALGORITHMS; POWER ELECTRONICS;

CANONICAL REPRESENTATION; FORMAL METHODOLOGY; HIERARCHICAL DESIGN EXPLORATION; PROBABILISTIC POWER PERFORMANCE;

PROBABILISTIC LOGICS;

EID: 33750918134     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127962     Document Type: Conference Paper

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