Timing and design closure in physical design flows

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 511-516

  Coudert, O ^a  

^a Monterey Design Systems   (United States)

Author keywords

Capacitance; Clocks; Crosstalk; Delay estimation; Logic; Routing; Signal design; Signal synthesis; Timing; Wire

Indexed keywords

CAPACITANCE; CLOCKS; CROSSTALK; WIRE;

DELAY ESTIMATION; LOGIC; ROUTING; SIGNAL DESIGN; SIGNAL SYNTHESIS; TIMING;

DESIGN;

EID: 4444321261     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996796     Document Type: Conference Paper

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