Gate resizing technique for high reduction in power consumption

International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1997, Pages 281-286

  Girard, P ^a   Landrault, C ^a   Pravossoudovitch, S ^a   Severac, D ^a  

^a UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; DIGITAL CIRCUITS; GATES (TRANSISTOR); INTEGER PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; SWITCHING;

GATE RESIZING TECHNIQUE; POST MAPPING TECHNIQUE; SIMPLEX METHOD;

VLSI CIRCUITS;

EID: 0030689996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)