-
1
-
-
0034480932
-
Test of Future System-on-Chips
-
November
-
Y. Zorian, S. Dey and M. J. Rodgers, "Test of Future System-on-Chips", International Conference on Computer Aided Design, pp. 392-398, November, 2000.
-
(2000)
International Conference on Computer Aided Design
, pp. 392-398
-
-
Zorian, Y.1
Dey, S.2
Rodgers, M.J.3
-
2
-
-
84942944391
-
Testing System Chips: Methodologies and Experiences
-
September
-
S. Dey, E. J. Marinissen and Y. Zorian, "Testing System Chips: Methodologies and Experiences", Integrated System Design, Vol. 11, No. 123, pp. 36-48, September, 1999.
-
(1999)
Integrated System Design
, vol.11
, Issue.123
, pp. 36-48
-
-
Dey, S.1
Marinissen, E.J.2
Zorian, Y.3
-
3
-
-
0033332425
-
Trends in SLI Design and their Effect on Test
-
September
-
R. Aiken and F. Muradali, "Trends in SLI Design and their Effect on Test", Proceedings of IEEE International Test Conference 1999 (ITC'99), Atlantic City, NJ, pp. 628-637, September, 1999.
-
(1999)
Proceedings of IEEE International Test Conference 1999 (ITC'99), Atlantic City, NJ
, pp. 628-637
-
-
Aiken, R.1
Muradali, F.2
-
4
-
-
0034484423
-
HD2BIST: A hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs
-
October
-
A. Benso, S. Chiusano, S. Di Carlo, P. Prinetto, F. Ricciato, M. Spadari and Y. Zorian, "HD2BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs", Proceedings of the International Test Conference, pp. 892-901, October, 2000.
-
(2000)
Proceedings of the International Test Conference
, pp. 892-901
-
-
Benso, A.1
Chiusano, S.2
Di Carlo, S.3
Prinetto, P.4
Ricciato, F.5
Spadari, M.6
Zorian, Y.7
-
6
-
-
0003387495
-
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
-
999 (DAC'99), October
-
A. Jas and N. Touba, "Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip", Proceedings of 1999 International Conference on Computer Design (ICCD'99), Austin, TX,. 999 (DAC'99), pp. 586-591, October, 1999.
-
(1999)
Proceedings of 1999 International Conference on Computer Design (ICCD'99), Austin, TX
, pp. 586-591
-
-
Jas, A.1
Touba, N.2
-
7
-
-
3142748928
-
Validation and Test of Systems on Chip: A Case Study
-
September
-
L. Balado and E. Lupon, "Validation and Test of Systems on Chip: A Case Study", Proceedings of 12th Annual IEEE International ASIC/SOC Conference, Washington, DC, pp. 238-242, September, 1999.
-
(1999)
Proceedings of 12th Annual IEEE International ASIC/SOC Conference, Washington, DC
, pp. 238-242
-
-
Balado, L.1
Lupon, E.2
-
8
-
-
0035272504
-
Software-Based Self-Testing Methodology for Processor Cores
-
March
-
L. Chen and S. Dey, "Software-Based Self-Testing Methodology for Processor Cores", IEEE Trans. Computer-Aided Designs, Vol.20, No.3, pp. 369-380, March, 2001.
-
(2001)
IEEE Trans. Computer-Aided Designs
, vol.20
, Issue.3
, pp. 369-380
-
-
Chen, L.1
Dey, S.2
-
9
-
-
0032640869
-
Microprocessor Based Testing for Core-Based System on Chip
-
C. A. Papachristou, F. Martin and M. Nourani, "Microprocessor Based Testing for Core-Based System on Chip", Proceedings of Design Automation Conference, (DAC'99), pp. 586-591, 1999.
-
(1999)
Proceedings of Design Automation Conference, (DAC'99)
, pp. 586-591
-
-
Papachristou, C.A.1
Martin, F.2
Nourani, M.3
-
11
-
-
0030215983
-
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
-
August
-
S. Gupta, J. Rajski and J. Tyszer, "Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns", IEEE Transactions on Computers, Vol. 45, No. 8, August 1996.
-
(1996)
IEEE Transactions on Computers
, vol.45
, Issue.8
-
-
Gupta, S.1
Rajski, J.2
Tyszer, J.3
-
12
-
-
0030660819
-
Test length reduction for accumulator-based self-test
-
F. Mayer, A.P. Stroele, "Test length reduction for accumulator-based self-test", Proceedings of 1997 IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 2705-2708, 1997.
-
(1997)
Proceedings of 1997 IEEE International Symposium on Circuits and Systems
, vol.4
, pp. 2705-2708
-
-
Mayer, F.1
Stroele, A.P.2
-
13
-
-
0034476674
-
Non-intrusive BIST for Systems-on-a-chip
-
October
-
S. Chiusano, P. Prinetto and H. J. Wunderlich, "Non-intrusive BIST for Systems-on-a-chip", Proceedings of the International Test Conference, pp. 644-651, October, 2000.
-
(2000)
Proceedings of the International Test Conference
, pp. 644-651
-
-
Chiusano, S.1
Prinetto, P.2
Wunderlich, H.J.3
-
14
-
-
3142671162
-
Optimal hardware pattern generation for functional BIST
-
March
-
S. Cataldo, S. Chiusano, P. Prinetto, and H.-J. Wunderlich, "Optimal hardware pattern generation for functional BIST", Proc. Meetings Design, Automation and Test Eur., Paris, France, pp. 292-297, March, 2000.
-
(2000)
Proc. Meetings Design, Automation and Test Eur., Paris, France
, pp. 292-297
-
-
Cataldo, S.1
Chiusano, S.2
Prinetto, P.3
Wunderlich, H.-J.4
-
15
-
-
0009022223
-
On Applying the Set Covering Model to Reseeding
-
S. Chiusano, S. Di Carlo, P. Prinetto, and H. J. Wunderlich, "On Applying the Set Covering Model to Reseeding", Proceedings of Design, Automation & Test in Europe Conference, pp. 156-160, 2001.
-
(2001)
Proceedings of Design, Automation & Test in Europe Conference
, pp. 156-160
-
-
Chiusano, S.1
Di Carlo, S.2
Prinetto, P.3
Wunderlich, H.J.4
-
16
-
-
0036605298
-
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
-
E. Kalligeros, X. Kavousianos, D. Bakalis and D. Nikolos, "On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST", Journal of Electronic Testing: Theory and Applications, 18, pp.315-332, 2002.
-
(2002)
Journal of Electronic Testing: Theory and Applications
, vol.18
, pp. 315-332
-
-
Kalligeros, E.1
Kavousianos, X.2
Bakalis, D.3
Nikolos, D.4
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