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Volumn 2005, Issue , 2005, Pages 691-696

Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; MATHEMATICAL MODELS; PARAMETER ESTIMATION; SYSTEMS ANALYSIS;

EID: 33750309376     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560154     Document Type: Conference Paper
Times cited : (43)

References (17)
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  • 3
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    • Y. Massoud and Y. Ismail, "Grasping the Impact of On-Chip Inductance," IEEE Circuits and Devices Magazine, vol. 17, Issue 4, pp. 14-21, July 2001.
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  • 6
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    • Inductance calculations in a complex integrated circuit environment
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    • Ruehli, A.1
  • 9
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    • Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis
    • June
    • B. Krauter and S. Mehrotra, "Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis," in Proceedings of the 35th Design Automation Conference, June 1998, pp. 303-308.
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    • Krauter, B.1    Mehrotra, S.2
  • 10
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    • On the accuracy of return path assumption for loop inductance extraction for 0.1 /spl mu/m technology and beyond
    • March
    • S. Kim, Y. Massoud, and S. Wong, "On the accuracy of return path assumption for loop inductance extraction for 0.1 /spl mu/m technology and beyond," Proceedings of International Symposium on Quality Electronic Design, pp. 401-404, March 2003.
    • (2003) Proceedings of International Symposium on Quality Electronic Design , pp. 401-404
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  • 11
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    • Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
    • March
    • X. Huang, P. Restle, T. Bucelot, Y. Cao, T. J. King, and C. Hu, "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design," IEEE Journal of Solid-State Circuits, vol. 38, no. 3, pp. 457-463, March 2003.
    • (2003) IEEE Journal of Solid-state Circuits , vol.38 , Issue.3 , pp. 457-463
    • Huang, X.1    Restle, P.2    Bucelot, T.3    Cao, Y.4    King, T.J.5    Hu, C.6
  • 13
    • 0033875648 scopus 로고    scopus 로고
    • Physical modeling of spiral inductors on silicon
    • March
    • C. Yue and S. Wong, "Physical Modeling of Spiral Inductors on Silicon," IEEE Transactions on Electron Devices, pp. 560-568, March 2000.
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  • 14
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    • Analytical formula for inductance of metal of various widths in spiral inductors
    • August
    • H.-M. Hsu, "Analytical Formula for Inductance of Metal of Various Widths in Spiral Inductors," IEEE Transactions on Electron Devices, vol. 51, no. 8, pp. 1343-1346, August 2004.
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    • Hsu, H.-M.1
  • 15
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    • An interior, trust region approach for nonlinear minimization subject to bounds
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.