On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 401-404

  Kim, So Young ^a   Massoud, Yehia ^b   Wong, S Simon ^a  

^a STANFORD UNIVERSITY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

Circuit noise; Circuit simulation; Computational modeling; Equations; Frequency; Inductance; Performance analysis; Timing; Wires; Working environment noise

Indexed keywords

CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; ELECTRIC NETWORK ANALYSIS; EXTRACTION; TIMING CIRCUITS; WIRE;

CIRCUIT NOISE; COMPUTATIONAL MODEL; EQUATIONS; FREQUENCY; PERFORMANCE ANALYSIS; TIMING; WORKING ENVIRONMENT;

INDUCTANCE;

EID: 84942119548     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194766     Document Type: Conference Paper

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