-
1
-
-
33749058763
-
Deconstructing and improving statistical simulation in HLS
-
June 20
-
R. H. Bell, Jr., L. Eeckhout, L. K. John and K. De Bosschere, "Deconstructing and Improving Statistical Simulation in HLS," Workshop on Debunking, Duplicating, and Deconstructing, in conjunction with ISCA'04, June 20, 2004.
-
(2004)
Workshop on Debunking, Duplicating, and Deconstructing, in Conjunction with ISCA'04
-
-
Bell Jr., R.H.1
Eeckhout, L.2
John, L.K.3
De Bosschere, K.4
-
2
-
-
33749045467
-
The case for automatic synthesis of miniature benchmarks
-
June 4
-
R. H. Bell, Jr. and L. K. John, "The Case for Automatic Synthesis of Miniature Benchmarks," Workshop on Modeling, Benchmarking, and Simulation, in conjunction with ISCA'05, June 4, 2005.
-
(2005)
Workshop on Modeling, Benchmarking, and Simulation, in Conjunction with ISCA'05
-
-
Bell Jr., R.H.1
John, L.K.2
-
5
-
-
0032069891
-
Calibration of microprocessor performance models
-
May
-
B. Black and J. P. Shen, "Calibration of Microprocessor Performance Models," IEEE Computer, May 1998, pp. 59-65.
-
(1998)
IEEE Computer
, pp. 59-65
-
-
Black, B.1
Shen, J.P.2
-
6
-
-
0032070245
-
Performance analysis and its impact on design
-
May
-
P. Bose and T. M. Conte, "Performance Analysis and Its Impact on Design," IEEE Computer, May 1998, pp. 41-49.
-
(1998)
IEEE Computer
, pp. 41-49
-
-
Bose, P.1
Conte, T.M.2
-
11
-
-
4644258856
-
Control flow modeling in statistical simulation for accurate and efficient processor design studies
-
June
-
L. Eeckhout, R. H. Bell, Jr., B. Stougie, L. K. John and K. De Bosschere, "Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies," International Symposium on Computer Architecture, June 2004.
-
(2004)
International Symposium on Computer Architecture
-
-
Eeckhout, L.1
Bell Jr., R.H.2
Stougie, B.3
John, L.K.4
De Bosschere, K.5
-
14
-
-
0032204476
-
Microprocessor power estimation using profile-driven program synthesis
-
November
-
C. T. Hsieh and M. Pedram, "Microprocessor Power Estimation Using Profile-driven Program Synthesis," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, November 1998, pp. 1080-1089.
-
(1998)
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
, vol.17
, Issue.11
, pp. 1080-1089
-
-
Hsieh, C.T.1
Pedram, M.2
-
15
-
-
0034312339
-
A performance methodology for commercial servers
-
November
-
S. R. Kunkel, R. J. Eickemeyer, M. H. Lipasti, T. J. Mullins, B. O'Krafka, H. Rosenberg, S. P. VanderWiel, P. L. Vitale and L. D. Whitley, "A Performance Methodology for Commercial Servers," IBM J. Res. Develp., Vol. 44 No. 6, November 2000.
-
(2000)
IBM J. Res. Develp.
, vol.44
, Issue.6
-
-
Kunkel, S.R.1
Eickemeyer, R.J.2
Lipasti, M.H.3
Mullins, T.J.4
O'Krafka, B.5
Rosenberg, H.6
VanderWiel, S.P.7
Vitale, P.L.8
Whitley, L.D.9
-
18
-
-
85084160699
-
Lmbench: Portable tools for performance analysis
-
Jan. 22-26
-
L. McVoy, "lmbench: Portable Tools for Performance Analysis," USENIX Technical Conference, Jan. 22-26, 1996, pp. 279-294.
-
(1996)
USENIX Technical Conference
, pp. 279-294
-
-
McVoy, L.1
-
20
-
-
84859292984
-
-
http://www.cs.washington.edu/homes/oskin/tools.html
-
-
-
-
22
-
-
33744471950
-
Intrinsic checkpointing: A methodology for decreasing simulation time through binary modification
-
March
-
J. Ringenberg, C. Pelosi, D. Oehmke and T. Mudge, "Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification," International Symposium on Performance and Simulation Systems, March 2005, pp. 78-88.
-
(2005)
International Symposium on Performance and Simulation Systems
, pp. 78-88
-
-
Ringenberg, J.1
Pelosi, C.2
Oehmke, D.3
Mudge, T.4
-
23
-
-
0242519839
-
Reverse tracer: A software tool for generating realistic performance test programs
-
M. Sakamoto, L. Brisson, A. Katsuno, A. Inoue and Y. Kimura, "Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs," Symposium on High-Performance Computing," 2002.
-
(2002)
Symposium on High-performance Computing
-
-
Sakamoto, M.1
Brisson, L.2
Katsuno, A.3
Inoue, A.4
Kimura, Y.5
-
25
-
-
28744440545
-
Performance analysis and validation of the Intel Pentium4 Processor on 90nm technology
-
R. Singhal, et al., "Performance Analysis and Validation of the Intel Pentium4 Processor on 90nm Technology," Intel Tech. J.,Vol. 8, No. 1, 2004.
-
(2004)
Intel Tech. J.
, vol.8
, Issue.1
-
-
Singhal, R.1
-
26
-
-
84859283704
-
-
http://www.spec.org
-
-
-
-
27
-
-
0036298603
-
POWER4 system microarchitecture
-
January
-
J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le and B. Sinharoy, "POWER4 System Microarchitecture," IBM Journal of Research and Development, January 2002, pp. 5-25.
-
(2002)
IBM Journal of Research and Development
, pp. 5-25
-
-
Tendler, J.M.1
Dodson, J.S.2
Fields Jr., J.S.3
Le, H.4
Sinharoy, B.5
-
29
-
-
0024032181
-
Benchmark synthesis using the LRU cache hit function
-
June
-
W. S. Wong and R. J. T. Morris, "Benchmark Synthesis Using the LRU Cache Hit Function," IEEE Transactions on Computers, Vol. 37, No. 6, June 1988, pp. 637-645.
-
(1988)
IEEE Transactions on Computers
, vol.37
, Issue.6
, pp. 637-645
-
-
Wong, W.S.1
Morris, R.J.T.2
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