메뉴 건너뛰기




Volumn , Issue , 2001, Pages 10-17

Early design phase power/performance modeling through statistical simulation

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; INTEGRATED CIRCUIT DESIGN;

EID: 84962135618     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2001.990669     Document Type: Conference Paper
Times cited : (18)

References (15)
  • 1
    • 0034316092 scopus 로고    scopus 로고
    • Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
    • November/December
    • D. Brooks, P. Bose, and et al. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors. IEEE Micro, 20(6):26-44, November/December 2000.
    • (2000) IEEE Micro , vol.20 , Issue.6 , pp. 26-44
    • Brooks, D.1    Bose, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.